A3P1000-FGG484 Actel, A3P1000-FGG484 Datasheet - Page 74
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A3P1000-FGG484
Manufacturer Part Number
A3P1000-FGG484
Description
FPGA - Field Programmable Gate Array 1M System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P1000-FGG484
Processor Series
A3P1000
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
300
Data Ram Size
147456
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
1000 K
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P1000-FGG484
Manufacturer:
FUJITSU
Quantity:
1 000
Company:
Part Number:
A3P1000-FGG484
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P1000-FGG484
Manufacturer:
ACTEL
Quantity:
20 000
Company:
Part Number:
A3P1000-FGG484I
Manufacturer:
ATMEL
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101
Company:
Part Number:
A3P1000-FGG484I
Manufacturer:
Microsemi SoC
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Part Number:
A3P1000-FGG484I
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Company:
Part Number:
A3P1000-FGG484T
Manufacturer:
Microsemi SoC
Quantity:
10 000
ProASIC3 DC and Switching Characteristics
Table 2-76 • Minimum and Maximum DC Input and Output Levels
Table 2-77 • Minimum and Maximum DC Input and Output Levels
2- 60
1.5 V
LVCMOS
Drive
Strength
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
1.5 V
LVCMOS
Drive
Strength
2 mA
4 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
12 mA
2 mA
4 mA
6 mA
8 mA
larger when operating outside recommended ranges
larger when operating outside recommended ranges
IL
IH
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < V
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
is the input leakage current per I/O pin over recommended operating conditions V
Min.
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
Min.
–0.3
Applicable to Advanced I/O Banks
–0.3
–0.3
–0.3
–0.3
Applicable to Standard Plus I/O Banks
V
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
V
VIL
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
VIL
Max.
Max.
V
V
0.65 * VCCI 1.575
0.65 * VCCI 1.575
0.65 * VCCI 1.575
0.65 * VCCI 1.575
0.65 * VCCI 1.575
Min.
V
Min.
V
VIH
VIH
Max.
V
Max.,
V
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI 12 12
Max.
VOL
R e visio n 9
V
Max.
VOL
V
VOH
Min.
V
VOH
Min.
V
mA mA
I
OL
2
4
mA mA
I
I
OL
OH
6
8
2
4
2
4
IH
< V
I
OH
6
8
2
4
Max.
mA
I
OSL
16
33
IN
Max.
mA
I
3
< V
OSL
16
33
39
55
55
3
IN
CCI
Max.
I
mA
< V
OSH
. Input current is
13
25
Max.
mA
I
OSH
13
25
32
66
66
IL
3
.
3
µA
µA
I
I
IL
10 10
10 10
10 10
10 10
10 10
IL
10 10
10 10
1
1
4
4
µA
µA
I
I
IH
IH
2
2
4
4