AGL1000V5-FGG256 Actel, AGL1000V5-FGG256 Datasheet - Page 104

• Manufacturer Part Number: AGL1000V5-FGG256
• Description: FPGA - Field Programmable Gate Array 1M System Gates IGLOO
• Manufacturer: Actel

Specifications of AGL1000V5-FGG256

• Processor Series: AGL1000
• Core: IP Core
• Maximum Operating Frequency: 892.86 MHz
• Number Of Programmable I/os: 177
• Data Ram Size: 147456
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1 M
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO DC and Switching Characteristics
Table 2-157 • Input Data Register Propagation Delays
Figure 2-19 • Output Register Timing Diagram
2- 90
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
Enable
DOUT
CLK
Preset
Clear
Data_out
For specific junction temperature and voltage supply levels, refer to
Output Register
Commercial-Case Conditions: T
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
1.2 V DC Core Voltage
50%
50%
t
1
OSUE
t
OHE
50%
50%
t
OSUD
0
t
t
OHD
OCLKQ
50%
50%
J
= 70°C, Worst-Case VCC = 1.14 V
50%
t
OWPRE
t
Description
OPRE2Q
50%
50%
R ev i sio n 1 8
t
t
ORECPRE
50%
OCLR2Q
50%
t
OWCLR
50%
50%
50%
Table 2-7 on page 2-7
t
ORECCLR
50%
t
OCKMPWH
t
50%
OREMPRE
for derating values.
t
50%
OCKMPWL
0.68
0.97
0.00
1.02
0.00
1.19
1.19
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
Std.
t
OREMCLR
50%
50%
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns