AGL600V2-FGG144 Actel, AGL600V2-FGG144 Datasheet - Page 63
![FPGA - Field Programmable Gate Array 600K System Gates](/photos/16/15/161502/landingpageacteligloofpga_sml.jpg)
AGL600V2-FGG144
Manufacturer Part Number
AGL600V2-FGG144
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL600V2-FGG144
Processor Series
AGL600
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
97
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL600V2-FGG144
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AGL600V2-FGG144I
Manufacturer:
ACTEL
Quantity:
101
Company:
Part Number:
AGL600V2-FGG144I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Table 2-64 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
Table 2-65 • 3.3 V LVCMOS Wide Range AC Waveforms, Measuring Points, and Capacitive Loads
3.3 V LVCMOS Wide
Range
Drive
Strength
100 µA
100 µA
100 µA
100 µA
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
2. I
3. I
4. Currents are measured at 100°C junction temperature and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
Input Low (V)
0
*
Measuring point = Vtrip. See
equivalent software default drive strength. These values are for normal ranges only
larger when operating outside recommended ranges
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
Applicable to Standard I/O Banks
Equivalent
Software
Strength
Option
Default
Drive
2 mA
4 mA
6 mA
8 mA
1
Min.
–0.3
–0.3
–0.3
–0.3
V
Table 2-28 on page 2-28
VIL
Max.
Input High (V)
0.8
0.8
0.8
0.8
V
3.3
Min.
V
2
2
2
2
VIH
Max.
3.6
3.6
3.6
3.6
V
for a complete table of trip points.
Max.
R ev i si o n 1 8
V
0.2
0.2
0.2
0.2
V
OL
Measuring Point* (V)
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
VOH
Min.
V
1.4
I
µA
OL
I
µA
OH
IGLOO Low Power Flash FPGAs
Max.
mA
TBD
TBD
TBD
TBD
I
OSL
4
C
LOAD
Max.
I
mA
TBD
TBD
TBD
TBD
OSH
5
4
(pF)
µA
I
IL
10
10
10
10
2
5
µA
I
2- 49
IH
10
10
10
10
3
5
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