A42MX16-TQG176 Actel, A42MX16-TQG176 Datasheet - Page 121

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A42MX16-TQG176

Manufacturer Part Number
A42MX16-TQG176
Description
FPGA - Field Programmable Gate Array 24K System Gates
Manufacturer
Actel
Datasheet

Specifications of A42MX16-TQG176

Processor Series
A42MX16
Core
IP Core
Number Of Macrocells
608
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
140
Delay Time
5.6 ns
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
3 V
Number Of Gates
24 K
Package / Case
TQFP-176
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version
(January 2004)
v6.0
v5.1
Changes in current version (v 6. 1 )
In
to -0.5 to V
In
min in industrial and military. V
The
The
The
The
The
The
Table 1 • Voltage Support of MX Devices
The
The
The
Figure 1-13 • Silicon Explorer II Setup with 42MX
Table 4 • Supported BST Public Instructions
Figure 1-14 • 42MX IEEE 1149.1 Boundary Scan Circuitry
Table 5 • Boundary Scan Pin Configuration and Functionality
The
The
Maximum Ratings for 40MX Devices*
The
The
In the
Ratings*,
Electrical
The
The
The <zBlue>Junction Temperature (TJ) section,
tables were updated.
The
The
The
The
The
Figure 1-17 • 40MX Timing Model*
Figure 1-19 • 42MX Timing Model (Logic Functions Using Quadrant Clocks)
Table 16 • Mixed 5.0V/3.3V Electrical
Table 14 • Absolute Maximum
"Ease of Integration" section
"Temperature Grade Offerings" section
"Speed Grade Offerings" section
"General Description" section
"MultiPlex I/O Modules" section
"User Security" section
"Power Dissipation" section
"Static Power Component" section
"Equivalent Capacitance" section
"Development Tool Support" section
Table 9 • 5V TTL Electrical Specifications
Table 13 • 3.3V LVTTL Electrical Specifications
Table 17 • DC Specification (5.0V PCI Signaling)1
Table 19 • DC Specification (3.3V PCI Signaling)1
Figure 1-20 • 42MX Timing Model (SRAM Functions)
Figure 1-27 • Output Buffer Latches
Table 22 • 42MX Temperature and Voltage Derating Factors
Table 23 • 40MX Temperature and Voltage Derating Factors
"Pin Descriptions" section
Table 7 • Absolute Maximum Ratings for 42MX Devices*
"Mixed 5.0V/3.3V Electrical Specifications"
Specificationswere updated.
Table 15 • Recommended Operating
CCA
+0.5.
was updated.
IH
was updated.
was updated.
had V
was updated.
was updated.
Ratings*, the limits in VI were changed from -0.5 to V
was updated.
is new.
was updated.
were updated.
was updated.
CCI
was updated.
Specifications, V
was updated.
was updated.
v6.1
was updated.
and that was changed to V
is new.
was updated.
was updated.
"Package Thermal Characteristics"
Conditions, and
was updated.
was updated.
was updated.
was updated.
section,
OH
was updated.
was updated.
was changed from 3.7 to 2.4 for the
was updated.
Table 14 • Absolute Maximum
is new.
is new.
and the
Table 16 • Mixed 5.0V/3.3V
CCA
.
FPGA Families 40MX and 42MX
Table 6 • Absolute
section, and the
CCI
+0.5
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