AGL400V2-FGG144 Actel, AGL400V2-FGG144 Datasheet - Page 76

FPGA - Field Programmable Gate Array 400K System Gates

AGL400V2-FGG144

Manufacturer Part Number
AGL400V2-FGG144
Description
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer
Actel
Datasheet

Specifications of AGL400V2-FGG144

Processor Series
AGL400
Core
IP Core
Number Of Logic Blocks
12
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
97
Data Ram Size
54 Kbit
Supply Voltage (max)
1.5 V
Supply Current
27 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.2 V
Number Of Gates
400 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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IGLOO DC and Switching Characteristics
Table 2-94 • Minimum and Maximum DC Input and Output Levels
Table 2-95 • Minimum and Maximum DC Input and Output Levels
2- 62
1.8 V
LVCMOS
Drive
Strength
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Notes:
1. I
2. I
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
1.8 V
LVCMOS
Drive
Strength
2 mA
4 mA
6 mA
8 mA
Notes:
1. I
2. I
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
larger when operating outside recommended ranges
larger when operating outside recommended ranges
IL
IH
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
Min.
Min.
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
V
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
V
Applicable to Advanced I/O Banks
Applicable to Standard Plus I/O Banks
VIL
VIL
0.35 * VCCI 0.65 * VCCI
Max.
Max.
V
V
Min.
Min.
V
V
VIH
VIH
Max.
Max.
1.9
1.9
1.9
1.9
1.9
1.9
1.9
1.9
1.9
1.9
V
V
Max.
VOL
Max.
VOL
0.45
0.45
0.45
0.45
0.45
0.45
0.45
0.45
0.45
0.45
V
V
R ev i sio n 1 8
VCCI – 0.45
VCCI – 0.45
VCCI – 0.45 6
VCCI – 0.45
VCCI – 0.45 12 12
VCCI – 0.45 16 16
VCCI – 0.45
VCCI – 0.45
VCCI – 0.45 6
VCCI – 0.45
VOH
Min.
VOH
Min.
V
V
mA mA
I
mA mA
I
OL
OL
2
4
8
4
2
8
I
I
OH
OH
6
6
2
4
8
2
4
8
Max.
I
mA
Max.
mA
I
OSH
OSH
17
35
45
91
91
17
35
35
9
9
3
3
Max.
mA
Max.
I
mA
I
OSL
22
44
51
74
74
OSL
11
11
22
44
44
3
3
µA
µA
I
I
10
IL
10
10
10
10
10
10
IL
10
10
10
1
1
4
4
µA
µA
I
I
IH
10
10
10
10
10
10
10
IH
10
10
10
2
2
4
4

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