LFXP6C-4TN144I Lattice, LFXP6C-4TN144I Datasheet - Page 17
LFXP6C-4TN144I
Manufacturer Part Number
LFXP6C-4TN144I
Description
FPGA - Field Programmable Gate Array 5.8K LUTs 100 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer
Lattice
Specifications of LFXP6C-4TN144I
Number Of Programmable I/os
100
Data Ram Size
73728
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-4TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 17 of 130
- Download datasheet (2Mb)
Lattice Semiconductor
Figure 2-15. Memory Core Reset
For further information on sysMEM EBR block, see the details of additional technical documentation at the end of
this data sheet.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-16. The GSR input to the
EBR is always asynchronous.
Figure 2-16. EBR Asynchronous Reset (Including GSR) Timing Diagram
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during
device Wake Up must occur before the release of the device I/Os becoming active.
These instructions apply to all EBR RAM and ROM implementations.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
Programmable I/O Cells (PICs)
Each PIC contains two PIOs connected to their respective sysIO Buffers which are then connected to the PADs as
shown in Figure 2-17. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysIO
buffer, and receives input from the buffer.
GSRN
RSTA
RSTB
Programmable Disable
Reset
Clock
Clock
Enable
Memory Core
2-14
Output Data
L
L
D
D
Latches
CLR
CLR
SET
SET
Q
Q
LatticeXP Family Data Sheet
Port A[17:0]
Port B[17:0]
MAX
(EBR clock). The reset
Architecture
Related parts for LFXP6C-4TN144I
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 142 IO 1.8 /2.5/3.3V -4 Spd
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 188 I/O 1.8/2.5/3.3V -4 Spd
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 100 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 100 IO 1.8 /2.5/3.3V -4 Spd
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 142 IO 1.8 /2.5/3.3V -4 Spd
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 142 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer:
Lattice
Part Number:
Description:
IC FPGA 5.8KLUTS 188I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTS 142 I/O
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTS 100 I/O
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA, 1.8V FLASH, INSTANT ON, SMD
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
Part Number:
Description:
FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 256-Pin FBGA Tray
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
Part Number:
Description:
FPGA LatticeXP Family 6000 Cells 400MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 256-Pin FBGA Tray
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
Part Number:
Description:
FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
Manufacturer:
Lattice
Datasheet: