LFXP2-8E-5TN144C Lattice, LFXP2-8E-5TN144C Datasheet - Page 92

• Manufacturer Part Number: LFXP2-8E-5TN144C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 100I/O Inst- on DSP 1.2V -5 Spd
• Manufacturer: Lattice
• Series: LatticeXP2r

Specifications of LFXP2-8E-5TN144C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 100
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• No. Of Logic Blocks: 8000
• No. Of Macrocells: 4000
• Family Type: LatticeXP2
• No. Of Speed Grades: 5
• Total Ram Bits: 221Kbit
• No. Of I/o's: 100
• Clock Management: PLL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
August 2008
June 2008
April 2008
April 2011
(cont.)
Date
Version
(cont.)
01.4
01.5
01.6
01.7
Characteristics (cont.)
Ordering Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
DC and Switching
DC and Switching
Characteristics
Characteristics
Characteristics
Architecture
Architecture
Section
—
Updated Flash Download Time (From On-Chip Flash to SRAM) Table
Updated Flash Program Time Table
Updated Flash Erase Time Table
Updated FlashBAK (from EBR to Flash) Table
Updated Hot Socketing Specifications Table footnotes
Updated Signal Descriptions Table
Removed Read-Before-Write sysMEM EBR mode.
Clarification of the operation of the secondary clock regions.
Removed Read-Before-Write sysMEM EBR mode.
Updated DDR Banks Bonding Out per I/O Bank section of Pin Informa-
tion Summary Table.
Data sheet status changed from preliminary to final.
Clarification of the operation of the secondary clock regions.
Removed “8W” specification from Hot Socketing Specifications table.
Removed "8W" footnote from DC Electrical Characteristics table.
Updated Register-to-Register Performance table.
Removed “8W” option from Part Number Description.
Removed XP2-17 “8W” OPNs.
Recommended Operating Conditions table, added footnote 5.
On-Chip Flash Memory Specifications table, added footnote 1.
BLVDS DC Conditions, corrected column title to be Z0 = 90 ohms.
sysCONFIG Port Timing Specifications table, added footnote 1 for 
t
DINIT
.
7-2
Change Summary
LatticeXP2 Family Data Sheet
Revision History