A3P125-PQG208 Actel, A3P125-PQG208 Datasheet - Page 88
A3P125-PQG208
Manufacturer Part Number
A3P125-PQG208
Description
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P125-PQG208
Processor Series
A3P125
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
133
Data Ram Size
36864
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
125 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P125-PQG208
Manufacturer:
ACT
Quantity:
5
Part Number:
A3P125-PQG208
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Company:
Part Number:
A3P125-PQG208I
Manufacturer:
Microsemi SoC
Quantity:
10 000
- Current page: 88 of 218
- Download datasheet (7Mb)
ProASIC3 DC and Switching Characteristics
Table 2-97 • Parameter Definition and Measuring Nodes
2- 74
Parameter Name
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
*
OCLKQ
OSUD
OHD
OSUE
OHE
OCLR2Q
OREMCLR
ORECCLR
OECLKQ
OESUD
OEHD
OESUE
OEHE
OECLR2Q
OEREMCLR
OERECCLR
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IREMCLR
IRECCLR
See
Figure 2-15 on page 2-73
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
for more information.
Parameter Definition
R e visio n 9
Measuring Nodes
(from, to)*
HH, DOUT
HH, EOUT
LL, DOUT
II, EOUT
GG, HH
GG, HH
CC, AA
DD, AA
KK, HH
KK, HH
AA, EE
CC, AA
BB, AA
DD, EE
DD, AA
FF, HH
FF, HH
LL, HH
LL, HH
BB, AA
JJ, HH
JJ, HH
II, HH
II, HH
Related parts for A3P125-PQG208
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
A3P125-FG144I
Manufacturer:
Actel
Datasheet:
Part Number:
Description:
FG144/I/A3P125-FGG144I
Manufacturer:
Actel
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer:
Actel
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer:
Actel
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer:
Actel
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer:
Actel
Datasheet:
Part Number:
Description:
QFN 132/FPGA, 3072 CLBS, 125000 GATES, 350 MHz
Manufacturer:
Actel
Part Number:
Description:
PQFP 100/FPGA, 3072 CLBS, 125000 GATES, 350 MHz
Manufacturer:
Actel