A3P600L-FGG256 Actel, A3P600L-FGG256 Datasheet - Page 2
A3P600L-FGG256
Manufacturer Part Number
A3P600L-FGG256
Description
FPGA - Field Programmable Gate Array 6K SYSTEM GATES
Manufacturer
Actel
Datasheet
1.A3P250L-VQG100.pdf
(224 pages)
Specifications of A3P600L-FGG256
Processor Series
A3P600
Core
IP Core
Maximum Operating Frequency
781.25 MHz
Number Of Programmable I/os
177
Data Ram Size
110592
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P600L-FGG256
Manufacturer:
ACT
Quantity:
24
Company:
Part Number:
A3P600L-FGG256
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A3P600L-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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I/Os Per Package
Table 2 • ProASIC3L FPGAs Package Sizes Dimensions
ProASIC3L
Low-Power
Devices
ARM
Cortex-M1
Devices
Package
VQ100
PQ208
FG144
FG256
FG324
FG484
FG896
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to
2. For A3P250L devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15.
3. ARM Cortex-M1 support is TBD on this device.
4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
5. FG256 and FG484 are footprint-compatible packages.
6. "G" indicates RoHS-compliant packages. Refer to
7. For A3PE3000L devices, the usage of certain I/O standards is limited as follows:
8. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended
Package
Length × Width
(mm\mm)
Nominal Area
(mm
Pitch (mm)
Height (mm)
ProASIC3L Low Power Flash FPGAs
I I
ensure you are complying with design and board migration requirements.
part number.
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
user I/Os available is reduced by one.
2
)
Ended I/O
Single-
151
157
68
97
–
–
–
A3P250L
4
Differential
14 × 14
VQ100
I/O Pairs
1.00
196
0.5
2
1
13
34
24
38
–
–
–
Ended I/O
28 × 28
PQ208
Single-
3.40
784
0.5
154
177
235
97
–
–
M1A3P600L
A3P600L
"ProASIC3L Ordering Information" on page III
4
Differential
13 × 13
I/O Pairs
FG144
R ev i si o n 9
1.45
169
1.0
35
25
43
60
–
–
–
I/O Type
Ended I/O
17 × 17
FG256
Single-
1.60
289
1.0
154
177
300
97
–
–
–
M1A3P1000L
A3P1000L
4
Differential
I/O Pairs
19 × 19
FG324
1.63
361
1.0
35
25
44
74
–
–
–
for the location of the "G" in the
Ended I/O
23 × 23
Single-
FG484
2.23
529
147
221
341
620
1.0
M1A3PE3000L
–
–
A3PE3000L
4
Differential
I/O Pairs
31 × 31
FG896
2.23
110
168
310
961
1.0
65
–
–
3
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