A42MX09-PLG84 Actel, A42MX09-PLG84 Datasheet - Page 46
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A42MX09-PLG84
Manufacturer Part Number
A42MX09-PLG84
Description
FPGA - Field Programmable Gate Array 14K System Gates
Manufacturer
Actel
Datasheet
1.A40MX04-PLG44.pdf
(124 pages)
Specifications of A42MX09-PLG84
Processor Series
A42MX09
Core
IP Core
Number Of Macrocells
336
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
104
Delay Time
5.6 ns
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
3 V
Number Of Gates
14 K
Package / Case
PLCC-84
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A42MX09-PLG84
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Company:
Part Number:
A42MX09-PLG84A
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A42MX09-PLG84I
Manufacturer:
NXP
Quantity:
12 000
Company:
Part Number:
A42MX09-PLG84I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 29 •
1 -4 0
Parameter Description
Input Module Predicted Routing Delays
t
t
t
t
t
Global Clock Network
t
t
t
t
t
t
f
TTL Output Module Timing
t
t
t
t
t
t
d
d
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
4. Delays based on 35 pF loading.
IRD1
IRD2
IRD3
IRD4
IRD8
CKH
CKL
PWH
PWL
CKSW
P
MAX
DLH
DHL
ENZH
ENZL
ENHZ
ENLZ
TLH
THL
40MX and 42MX FPGA Families
device performance. Post-route timing analysis or simulation is required to determine actual performance.
time for this macro.
A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Input LOW to HIGH
Input HIGH to LOW
Minimum Pulse
Width HIGH
Minimum Pulse
Width LOW
Maximum Skew
Minimum Period
Maximum Frequency FO = 16
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
4
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 128
1
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
‘–3’ Speed
3.1
3.3
3.1
3.3
6.5
6.8
CC
0.04
11.1
0.03
113
109
2.9
3.6
4.4
5.1
8.0
6.4
6.4
6.7
6.7
0.6
0.8
4.7
5.6
5.2
6.6
8.2
= 3.0V, T
v6.1
‘–2’ Speed
3.6
3.8
3.6
3.8
7.5
7.8
J
= 70°C)
9.26
0.03
0.04
12.8
105
101
6.0
7.6
9.5
3.4
4.2
5.0
5.9
7.4
7.4
7.8
7.8
0.6
0.9
5.4
6.4
‘–1’ Speed
4.1
4.3
4.1
4.3
8.5
8.9
10.5
14.5
10.7
0.04
0.05
3.8
4.8
5.7
6.7
8.3
8.3
8.8
8.8
0.7
1.0
6.1
7.3
6.8
8.6
96
92
‘Std’ Speed
10.1
10.4
4.8
5.1
4.8
5.1
12.6
10.4
10.4
10.1
17.1
12.6
0.04
0.06
4.5
5.6
6.7
7.8
9.8
9.8
0.8
1.2
7.2
8.6
8.1
83
80
14.1
14.6
‘–F’ Speed
6.7
7.1
6.7
7.1
10.0
12.0
11.3
14.1
23.9
17.7
0.06
0.08
11.0
17.3
13.7
13.7
14.5
14.5
6.3
7.8
9.4
1.2
1.6
50
48
ns/pF
ns/pF
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns