LFXP10C-4FN256C Lattice, LFXP10C-4FN256C Datasheet - Page 21
![FPGA - Field Programmable Gate Array 9.7K LUTs 188 I/O 1.8/2.5/3.3V -4 Spd](/photos/16/14/161486/bga256_sml.jpg)
LFXP10C-4FN256C
Manufacturer Part Number
LFXP10C-4FN256C
Description
FPGA - Field Programmable Gate Array 9.7K LUTs 188 I/O 1.8/2.5/3.3V -4 Spd
Manufacturer
Lattice
Specifications of LFXP10C-4FN256C
Number Of Programmable I/os
188
Data Ram Size
221184
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP10C-4FN256C
Manufacturer:
LATTICE
Quantity:
73
Company:
Part Number:
LFXP10C-4FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-21. Input Register DDR Waveforms
Figure 2-22. INDDRXB Primitive
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysIO buffers. The block contains a register for SDR operation that is combined with an additional latch for
DDR operation. Figure 2-23 shows the diagram of the Output Register Block.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-
type or as a latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Figure 2-24 shows the design tool DDR primitives. The SDR output register has reset and clock enable available.
The additional register for DDR operation does not have reset or clock enable available.
(In DDR Mode)
Delayed
DQS
DQS
D0
D2
DI
DDRCLKPOL
A
ECLK
SCLK
LSR
CE
D
B
2-18
IDDRXB
C
B
A
QA
QB
D
LatticeXP Family Data Sheet
E
D
C
F
Architecture
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