LFXP2-17E-5FTN256C Lattice, LFXP2-17E-5FTN256C Datasheet - Page 34

• Manufacturer Part Number: LFXP2-17E-5FTN256C
• Description: FPGA - Field Programmable Gate Array 17K LUTs 201I/O DSP 1.2V -5 Speed
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FTN256C

• Number Of Macrocells: 17000
• Maximum Operating Frequency: 200 MHz
• Number Of Programmable I/os: 201
• Data Ram Size: 35 Kbit
• Supply Voltage (max): 1.14 V
• Supply Current: 28 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.26 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-28. DQS Input Routing (Left and Right)
Figure 2-29. DQS Input Routing (Top and Bottom)
DQS
DQS
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO B
PIO B
PIO B
PIO B
PIO B
PIO B
PIO B
PIO B
PIO B
PIO A
PIO A
PIO A
PIO A
PIO A
PIO A
PIO A
PIO A
PIO A
2-31
Buffer
sysIO
Delay
Buffer
Delay
sysIO
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
LatticeXP2 Family Data Sheet
PADB "C"
PADA "T"
PADB "C"
PADB "C"
PADA "T"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
DQS Pin
PADB "C"
Assigned
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
LVDS Pair
LVDS Pair
LVDS Pair
PADB "C"
PADA "T"
PADA "T"
PADB "C"
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
LVDS Pair
PADB "C"
DQS Pin
Assigned
PADA "T"
PADB "C"
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
Architecture