APA075-PQG208 Actel, APA075-PQG208 Datasheet - Page 39

• Manufacturer Part Number: APA075-PQG208
• Description: FPGA - Field Programmable Gate Array 75K System Gates
• Manufacturer: Actel

Specifications of APA075-PQG208

• Processor Series: APA075
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 158
• Data Ram Size: 27648
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 75 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Logic-Tile Contribution—P
P
where:
I/O Output Buffer Contribution—P
P
where:
I/O Input Buffer's Buffer Contribution—P
The input’s component of AC power dissipation is given by
where:
PLL Contribution—P
where:
RAM Contribution—P
Finally, P
where:
logic
outputs
P
P
P
P
P
P3
mc =
Fs
P4
C
p
Fp
P9
N
P6
N
F
E
, the logic-tile component of AC power dissipation, is given by
P8
q
Fq
logic
outputs
inputs
pll
memory
memory
memory
load
Pll
memory
, the I/O component of AC power dissipation, is given by
= P9 * N
memory
= P3 * mc * Fs
=
=
=
=
=
= P8 * q * Fq
= (P4 + (C
=
=
=
=
=
=
= P6 * N
1.4 μW/MHz is the average power consumption of a logic tile per MHz of its output toggling rate. The
maximum output toggling rate is Fs/2.
the number of logic tiles switching during each Fs cycle
the clock frequency
29 μW/MHz is the intrinsic power consumption of an input pad normalized per MHz of the input
frequency.
the number of inputs
the average input frequency
, the memory component of AC power consumption, is given by
326 μW/MHz is the intrinsic power consumption of an output pad normalized per MHz of the output
frequency. This is the total I/O current V
the output load
the number of outputs
the average output frequency
pll
7.5 mW. This value has been estimated at maximum PLL clock frequency.
number of PLLs used
=
=
=
=
memory
load
pll
175 µW/MHz is the average power consumption of a memory block per MHz of the clock
the number of RAM/FIFO blocks
(1 block = 256 words * 9 bits)
the clock frequency of the memory
the average number of active blocks divided by the total number of blocks (N) of the memory.
memory
* V
• Typical values for E
• In addition, an application-dependent component to E
* F
DDP
logic
9, 16, and 32 memory configuration
example, for a 1kx8 memory configuration using only 1 cycle out of 2, E
memory
2
)) * p * Fp
* E
outputs
memory
inputs
memory
DDP
would be 1/4 for a 1k x 8,9,16, 32 memory and 1/16 for a 4kx8,
v5.9
.
memory
ProASIC
can be considered. For
PLUS
memory
Flash Family FPGAs
= 1/4*1/2 = 1/8
2-29