LFX125EB-04FN256C Lattice, LFX125EB-04FN256C Datasheet - Page 62

• Manufacturer Part Number: LFX125EB-04FN256C
• Description: FPGA - Field Programmable Gate Array E-Ser139K Gt ispJTAG 2.5/3.3V -4 Spd
• Manufacturer: Lattice

Specifications of LFX125EB-04FN256C

• Number Of Macrocells: 1936
• Number Of Programmable I/os: 160
• Data Ram Size: 94208
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.65 V
• Number Of Gates: 139 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispXP sysCONFIG Port Timing Specifications
Boundary Scan Timing
t
t
t
t
t
t
t
t
t
t
t
t
t
t
sysCONFIG Write Cycle Timing
t
t
t
t
t
t
t
t
t
t
f
sysCONFIG Read Cycle Timing
t
t
t
t
f
t
BTCP
BTCPH
BTCPL
BTS
BTH
BTRF
BTCO
BTCODIS
BTCOEN
BTCRS
BTCRH
BUTCO
BTUODIS
BTUPOEN
SUCS
HCS
SUWD
HWD
PRGM
WINIT
IODISS
IOENSS
WH
WL
MAXW
HREAD
SUREAD
RH
RL
MAXR
CORD
Parameter
Symbol
TCK [BSCAN] Clock Pulse Width
TCK [BSCAN] Clock Pulse Width High
TCK [BSCAN] Clock Pulse Width Low
TCK [BSCAN] Setup Time
TCK [BSCAN] Hold Time
TCK [BSCAN] Rise/Fall Time
TAP Controller Falling Edge of Clock to Valid Output
TAP Controller Falling Edge of Clock to Valid Disable
TAP Controller Falling Edge of Clock to Valid Enable
BSCAN Test Capture Register Setup Time
BSCAN Test Capture Register Hold Time
BSCAN Test Update Register, Falling Edge of Clock to Valid Output
BSCAN Test Update Register, Falling Edge of Clock to Valid Disable
BSCAN Test Update Register, Falling Edge of Clock to Valid Enable
Input setup time of CS to CCLK rise
Hold time of CS to CCLK Rise
Input setup time of write data to CCLK rise
Hold time of write data to CCLK rise
Low time to reset device SRAM
INIT pulse width
User I/O disable
User I/O enable
Write clock High pulse width
Write clock Low pulse width
Write f
Hold time of READ to CCLK rise
Input setup time of READ High to CCLK rise
READ clock high pulse width
READ clock low pulse width
Read f
Clock to out for read data
MAX
MAX
Timing Parameter
Description
58
Min.
ispXPGA Family Data Sheet
10
12
12
12
30
12
15
—
—
—
—
—
—
0
0
5
0
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
40
20
20
10
50
25
—
—
—
—
—
—
8
8
Max.
50
30
30
33
33
25
—
—
—
—
—
—
—
—
—
—
5
Max.
18
18
18
45
20
20
—
—
—
—
—
—
—
—
Units
MHz
MHz
mV/ns
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns