A40MX04-PQG100 Actel, A40MX04-PQG100 Datasheet - Page 61

• Manufacturer Part Number: A40MX04-PQG100
• Description: FPGA - Field Programmable Gate Array 6K System Gates
• Manufacturer: Actel

Specifications of A40MX04-PQG100

• Processor Series: A40MX04
• Core: IP Core
• Number Of Macrocells: 547
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 69
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 6000
• Package / Case: PQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 33 •
Parameter Description
CMOS Output Module Timing
t
t
t
t
t
t
t
t
t
t
t
t
d
d
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
5. Delays based on 35 pF loading.
DLH
DHL
ENZH
ENZL
ENHZ
ENLZ
GLH
GHL
LSU
LH
LCO
ACO
TLH
THL
device performance. Post-route timing analysis or simulation is required to determine actual performance.
obtained from the Timer utility.
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
G-to-Pad LOW
I/O Latch Set-Up
I/O Latch Hold
I/O Latch Clock-to-Out (Pad-to-
Pad), 64 Clock Loading
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
Capacity Loading, LOW to HIGH
Capacity Loading, HIGH to LOW
PD1
5
+ t
RD1
+ t
PDn
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
‘–3’ Speed
0.7
0.0
, t
CO
CCA
+ t
12.2
0.04
0.05
3.4
4.1
3.7
4.1
6.9
7.5
5.8
5.8
8.7
RD1
= 3.0V, T
+ t
v6.1
‘–2’ Speed
PDn
0.8
0.0
, or t
J
= 70°C)
13.5
0.04
0.05
4.5
4.5
7.6
8.3
9.7
PD1
3.8
4.1
6.5
6.5
+ t
RD1
‘–1’ Speed
0.9
0.0
+ t
SUD
10.9
15.4
0.05
0.06
5.5
4.2
4.6
5.1
8.6
9.4
7.3
7.3
, whichever is appropriate.
‘Std’ Speed
1.0
0.0
40MX and 42MX FPGA Families
10.2
11.1
12.9
18.1
0.06
0.07
6.4
5.0
5.5
6.1
8.6
8.6
‘–F’ Speed
1.4
0.0
14.2
15.5
12.0
12.0
18.0
25.3
0.08
0.10
9.0
7.0
7.6
8.5
Units
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1-55