A42MX24-PQG208 Actel, A42MX24-PQG208 Datasheet - Page 7
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A42MX24-PQG208
Manufacturer Part Number
A42MX24-PQG208
Description
FPGA - Field Programmable Gate Array 36K System Gates
Manufacturer
Actel
Datasheet
1.A40MX04-PLG44.pdf
(124 pages)
Specifications of A42MX24-PQG208
Processor Series
A42MX24
Core
IP Core
Number Of Macrocells
912
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
140
Delay Time
5.6 ns
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
3 V
Number Of Gates
36 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A42MX24-PQG208
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A42MX24-PQG208A
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A42MX24-PQG208I
Manufacturer:
Microsemi SoC
Quantity:
10 000
40MX and 42MX FPGA Families
General Description
Actel's 40MX and 42MX families offer a cost-effective
design solution at 5V. The MX devices are single-chip
solutions
shortening the system design and development cycle.
MX
implemented in multiple PALs, CPLDs, and FPGAs.
Example applications include high-speed controllers and
address decoding, peripheral bus interfaces, DSP, and co-
processor functions.
The MX device architecture is based on Actel’s patented
antifuse technology implemented in a 0.45µm triple-
metal CMOS process. With capacities ranging from 3,000
to 54,000 system gates, the MX devices provide
performance up to 250 MHz, are live on power-up and
have one-fifth the standby power consumption of
comparable FPGAs. Actel’s MX FPGAs provide up to 202
user I/Os and are available in a wide variety of packages
and speed grades.
Actel’s A42MX24 and A42MX36 devices also feature
MultiPlex I/Os, which support mixed-voltage systems,
enable programmable PCI, deliver high-performance
operation at both 5.0V and 3.3V, and provide a low-
power mode. The devices are fully compliant with the
PCI Local Bus Specification (version 2.1). They deliver
200 MHz on-chip operation and 6.1 ns clock-to-output
performance.
The 42MX24 and 42MX36 devices include system-level
features such as IEEE Standard 1149.1 (JTAG) Boundary
Scan Testing and fast wide-decode modules. In addition,
the A42MX36 device offers dual-port SRAM for
implementing fast FIFOs, LIFOs, and temporary data
storage. The storage elements can efficiently address
applications requiring wide datapath manipulation and
can perform transformation functions such as those
required for telecommunications, networking, and DSP.
All MX devices are fully tested over automotive and
military temperature ranges. In addition, the largest
member of the family, the A42MX36, is available in both
CQ208 and CQ256 ceramic packages screened to MIL-
STD-883 levels. For easy prototyping and conversion from
plastic to ceramic, the CQ208 and PQ208 devices are pin-
compatible.
devices
and
can
provide
integrate
high
and
performance
consolidate
while
logic
v6.1
MX Architectural Overview
The MX devices are composed of fine-grained building
blocks that enable fast, efficient logic designs. All devices
within these families are composed of logic modules, I/O
modules, routing resources and clock networks, which
are the building blocks for fast logic designs. In addition,
the A42MX36 device contains embedded dual-port
SRAM modules, which are optimized for high-speed
datapath functions such as FIFOs, LIFOs and scratchpad
memory. A42MX24 and A42MX36 also contain wide-
decode modules.
Logic Modules
The 40MX logic module is an eight-input, one-output
logic circuit designed to implement a wide range of logic
functions with efficient use of interconnect routing
resources
The logic module can implement the four basic logic
functions (NAND, AND, OR and NOR) in gates of two,
three, or four inputs. The logic module can also
implement a variety of D-latches, exclusivity functions,
AND-ORs and OR-ANDs. No dedicated hard-wired latches
or flip-flops are required in the array; latches and flip-
flops can be constructed from logic modules whenever
required in the application.
Figure 1-1 • 40MX Logic Module
(Figure
1-1).
40MX and 42MX FPGA Families
1-1