PT7C4307WEX Pericom Semiconductor, PT7C4307WEX Datasheet - Page 7
![IC REAL TIME CLK/CALENDAR 8-SOIC](/photos/18/28/182870/8-soic_sml.jpg)
PT7C4307WEX
Manufacturer Part Number
PT7C4307WEX
Description
IC REAL TIME CLK/CALENDAR 8-SOIC
Manufacturer
Pericom Semiconductor
Type
Clock/Calendarr
Datasheet
1.PT7C4307WEX.pdf
(16 pages)
Specifications of PT7C4307WEX
Memory Size
56B
Time Format
Binary
Date Format
Binary
Interface
I²C, 2-Wire Serial
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PT7C4307WEXTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PT7C4307WEX
Manufacturer:
Pericom
Quantity:
4 200
Part Number:
PT7C4307WEX
Manufacturer:
PERICOM
Quantity:
20 000
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Note: Any registered imaginary time should be replaced by correct time, otherwise it will cause the clock counter malfunction.
I
Overview of I
The I
of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on.
Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and
stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data
transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the
data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per
clock pulse. The I
chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its
slave address matches the slave address in the received data.
System Configuration
All ports connected to the I
multiple devices.
SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high
level when the bus is released (when communication is not being performed).
PT0206(08/09)
Addr.
(hex)
2
C Bus Interface
Fig 1. System configuration
04
05
06
2
C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination
Note: When there is only one master, the MCU is ready for driving SCL to "H" and R
SDA
SCL
Vcc
Description
(default)
(default)
(default)
Months
Dates
Years
R
2
P
C-BUS
2
C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a
R
P
2
C bus must be either open drain or open collector ports in order to enable AND connections to
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Y80
D7
0
0
0
0
Master
MCU
Y40
D6
0
0
0
0
Undefined Undefined Undefined Undefined Undefined Undefined
D20
Y20
D5
0
0
Slave
RTC
7
Undefined Undefined Undefined Undefined Undefined
M10
D10
Y10
D4
Real-time Clock Module (I
M8
D3
D8
Y8
Other Peripheral
Device
P
of SCL may not required.
M4
D2
D4
Y4
M2
D1
D2
Y2
Data Sheet
PT7C4307
2
C Bus)
M1
D0
D1
Y1
Ver: 3