XC6VSX475T-2FFG1156I Xilinx Inc, XC6VSX475T-2FFG1156I Datasheet - Page 48

• Manufacturer Part Number: XC6VSX475T-2FFG1156I
• Description: IC FPGA VIRTEX 1156FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 SXTr

Specifications of XC6VSX475T-2FFG1156I

• Number Of Logic Elements/cells: 476160
• Number Of Labs/clbs: 37200
• Total Ram Bits: 39223296
• Number Of I /o: 600
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1156-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

MMCM Switching Characteristics
Table 63: MMCM Specification
DS152 (v3.2) April 1, 2011
Product Specification
F
F
F
F
F
F
F
F
F
T
T
T
T
F
F
T
RST
F
F
T
T
T
T
T
INMAX
INMIN
INJITTER
INDUTY
MIN_PSCLK
MAX_PSCLK
VCOMIN
VCOMAX
BANDWIDTH
STATPHAOFFSET
OUTJITTER
OUTDUTY
LOCKMAX
OUTMAX
OUTMIN
EXTFDVAR
PFDMAX
PFDMIN
FBDELAY
MMCMDCK_PSEN
MMCMCKD_PSEN
MMCMDCK_PSINCDEC
MMCMCKD_PSINCDEC
MINPULSE
(2)
Symbol
/
/
Maximum Input Clock Frequency
Minimum Input Clock Frequency
Maximum Input Clock Period Jitter
Allowable Input Duty Cycle: 10—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum Dynamic Phase Shift Clock Frequency
Maximum Dynamic Phase Shift Clock Frequency
Minimum MMCM VCO Frequency
Maximum MMCM VCO Frequency
Low MMCM Bandwidth at Typical
High MMCM Bandwidth at Typical
Static Phase Offset of the MMCM Outputs
MMCM Output Jitter
MMCM Output Clock Duty Cycle Precision
MMCM Maximum Lock Time
MMCM Maximum Output Frequency
MMCM Minimum Output Frequency
External Clock Feedback Variation
Minimum Reset Pulse Width
Maximum Frequency at the Phase Frequency
Detector with Bandwidth Set to High or Optimized
Maximum Frequency at the Phase Frequency
Detector with Bandwidth Set to Low
Minimum Frequency at the Phase Frequency
Detector with Bandwidth Set to High or Optimized
Minimum Frequency at the Phase Frequency
Detector with Bandwidth Set to Low
Maximum Delay in the Feedback Path
Setup and Hold of Phase Shift Enable
Setup and Hold of Phase Shift Increment/Decrement
Description
(5)
www.xilinx.com
(1)
(3)
(3)
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
(7)(8)
(4)
(6)
(9)
1600
0.01
1.00
4.00
0.12
0.15
4.69
1.04
0.00
1.04
0.00
800
550
600
100
800
550
300
135
1.5
10
10
-3
< 20% of clock input period or 1 ns Max
< 20% of clock input period or 1 ns Max
3 ns Max or one CLKIN cycle
1440
0.01
1.00
4.00
0.12
0.20
4.69
1.04
0.00
1.04
0.00
750
500
600
100
750
500
300
135
1.5
Speed Grade
10
10
-2
25/75
30/70
35/65
40/60
45/55
Note 1
1200
0.01
1.00
4.00
0.12
0.20
4.69
1.04
0.00
1.04
0.00
700
450
600
100
700
450
300
135
1.5
10
10
-1
1200
0.01
1.00
4.00
0.12
0.20
4.69
1.04
0.00
1.04
0.00
700
450
600
100
700
450
300
135
-1L
1.5
10
10
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
µs
ns
ns
ns
%
%
%
%
%
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