PIC16LF721-I/SS Microchip Technology, PIC16LF721-I/SS Datasheet - Page 20
![MCU PIC 4K FLASH 20-SSOP](/photos/19/6/190623/4696163_sml.jpg)
PIC16LF721-I/SS
Manufacturer Part Number
PIC16LF721-I/SS
Description
MCU PIC 4K FLASH 20-SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF721-I/SS
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
17
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP (0.200", 5.30mm Width)
Controller Family/series
PIC16LF
No. Of I/o's
18
Ram Memory Size
256Byte
Cpu Speed
16MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F/LF720/721
TABLE 2-1:
DS41430A-page 20
180h
181h
182h
183h
184h
185h
186h
187h
188h
18Ah
18Bh
18Ch
18Dh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
Legend:
Note 1:
Bank 3
Address
(
(
(
(
(
(
2
2
2
2
1
2
2:
3:
4:
5:
)
)
)
)
),(
)
2
)
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
These registers can be addressed from any bank.
Accessible only when SSPM<3:0> = 1001.
This bit is unimplemented and reads as ‘1’.
See
INDF
OPTION_
REG
PCL
STATUS
FSR
ANSELA
ANSELB
ANSELC
PCLATH
INTCON
PMCON1
PMCON2
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Register
Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
6-2.
RABPU
ANSC7
Bit 7
—
IRP
GIE
—
—
—
Addressing this location uses contents of FSR to address data memory (not a physical register)
(4)
INTEDG
ANSC6
CFGS
Bit 6
PEIE
RP1
—
—
—
Program Memory Control Register 2 (not a physical register)
TMR0IE
Program Counter (PC) Least Significant Byte
ANSB5
LWLO
T0CS
Bit 5
RP0
—
—
—
Indirect Data Memory Address Pointer
Write Buffer for the upper 5 bits of the Program Counter
ANSA4
ANSB4
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
FREE
T0SE
Bit 4
INTE
TO
—
ANSC3
RABIE
Bit 3
PSA
PD
—
—
—
TMR0IF
ANSA2
ANSC2
WREN
Bit 2
PS2
—
Z
ANSA1
ANSC1
2010 Microchip Technology Inc.
INTF
Bit 1
PS1
WR
DC
—
ANSA0
ANSC0
RABIF
Bit 0
PS0
RD
—
C
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
---1 -111
--11 ----
11-- 1111
---0 0000
0000 000x
1000 -000
---- ----
POR, BOR
Value on
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Value on all
xxxx xxxx
1111 1111
0000 0000
000q quuu
uuuu uuuu
---1 -111
--11 ----
11-- 1111
---0 0000
0000 000x
1000 -000
---- ----
Resets
other
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
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