PIC16LF721-I/ML Microchip Technology, PIC16LF721-I/ML Datasheet - Page 122
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PIC16LF721-I/ML
Manufacturer Part Number
PIC16LF721-I/ML
Description
MCU PIC 4K FLASH 20-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF721-I/ML
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
17
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VFQFN Exposed Pad
Controller Family/series
PIC16LF
No. Of I/o's
18
Ram Memory Size
256Byte
Cpu Speed
16MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F/LF720/721
16.1.1.4
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
16.1.1.5
The AUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set, the
AUSART will shift 9 bits out for each character transmit-
ted. The TX9D bit of the TXSTA register is the ninth,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the 8 Least Significant bits into the TXREG. All nine bits
of data will be transferred to the TSR shift register
immediately after the TXREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. Refer to
Detection”
FIGURE 16-3:
FIGURE 16-4:
DS41430A-page 122
Note:
Reg. Empty Flag)
Note:
Reg. Empty Flag)
Write to TXREG
(Transmit Buffer
Write to TXREG
(Transmit Shift
(Transmit Buffer
(Transmit Shift
BRG Output
(Shift Clock)
Empty Flag)
BRG Output
(Shift Clock)
Empty Flag)
TX/CK pin
TRMT bit
TX/CK pin
TRMT bit
TXIF bit
The TSR register is not mapped in data
memory, so it is not available to the user.
for more information on the Address mode.
TXIF bit
This timing diagram shows two consecutive transmissions.
TSR Status
Transmitting 9-Bit Characters
ASYNCHRONOUS TRANSMISSION
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
1 T
Word 1
Transmit Shift Reg
CY
Word 1
Transmit Shift Reg.
Word 1
Word 1
Section 16.1.2.7 “Address
1 T
CY
Start bit
Start bit
Word 2
1 T
CY
bit 0
bit 0
bit 1
Word 1
bit 1
Word 1
16.1.1.6
1.
2.
3.
4.
5.
6.
7.
Initialize the SPBRG register and the BRGH bit to
achieve the desired baud rate (Refer to
Section 16.2 “AUSART Baud Rate Generator
(BRG)”).
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If 9-bit transmission is desired, set the TX9 con-
trol bit. A set ninth data bit will indicate that the 8
Least Significant data bits are an address when
the receiver is set for address detection.
Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
Load 8-bit data into the TXREG register. This
will start the transmission.
Asynchronous Transmission Setup:
bit 7/8
bit 7/8
Word 2
Transmit Shift Reg.
2010 Microchip Technology Inc.
Stop bit
Stop bit
Start bit
Word 2
bit 0
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