PIC16LF1527-I/MR Microchip Technology, PIC16LF1527-I/MR Datasheet - Page 84
![MCU PIC 28KB FLASH 64QFN](/photos/16/3/160368/qfn64_sml.jpg)
PIC16LF1527-I/MR
Manufacturer Part Number
PIC16LF1527-I/MR
Description
MCU PIC 28KB FLASH 64QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16LF1526T-IPT.pdf
(354 pages)
Specifications of PIC16LF1527-I/MR
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
28KB (16K x 14)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN Exposed Pad
Processor Series
PIC16F
Core
PIC
Data Ram Size
768 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
9
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (3Mb)
PIC16(L)F1526/27
7.6.5
The PIE4 register contains the interrupt enable bits, as
shown in
REGISTER 7-5:
DS41458A-page 84
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CCP10IE
R/W-0/0
Register
PIE4 REGISTER
CCP10IE: CCP10 Interrupt Enable bit
1 = Enables the CCP10 interrupt
0 = Disables the CCP10 interrupt
CCP9IE: CCP9 Interrupt Enable bit
1 = Enables the CCP9 interrupt
0 = Disables the CCP9 interrupt
RC2IE: USART2 Receive Interrupt Enable bit
1 = Enables the USART2 receive interrupt
0 = Disables the USART2 receive interrupt
TX2IE: USART2 Transmit Interrupt Enable bit
1 = Enables the USART2 transmit interrupt
0 = Disables the USART2 transmit interrupt
CCP8IE: CCP8 Interrupt Enable bit
1 = Enables the CCP8 interrupt
0 = Disables the CCP8 interrupt
CCP7IE: CCP7 Interrupt Enable bit
1 = Enables the CCP7 interrupt
0 = Disables the CCP7 interrupt
BCL2IE: MSSP2 Bus Collision Interrupt Enable bit
1 = Enables the MSSP2 Bus Collision Interrupt
0 = Disables the MSSP2 Bus Collision Interrupt
SSP2IE: Synchronous Serial Port (MSSP2) Interrupt Enable bit
1 = Enables the MSSP2 interrupt
0 = Disables the MSSP2 interrupt
7-5.
R/W-0/0
CCP9IE
PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
RC2IE
R-0/0
TX2IE
R-0/0
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
CCP8IE
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
R/W-0/0
CCP7IE
2011 Microchip Technology Inc.
R/W-0/0
BCL2IE
R/W-0/0
SSP2IE
bit 0
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