PIC18F25K80-I/SS Microchip Technology, PIC18F25K80-I/SS Datasheet - Page 444
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PIC18F25K80-I/SS
Manufacturer Part Number
PIC18F25K80-I/SS
Description
MCU PIC 32KB FLASH 28SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F25K80-I/SS
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP (0.200", 5.30mm Width)
Controller Family/series
PIC18
Ram Memory Size
4KB
Cpu Speed
16MIPS
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, USART
Processor Series
PIC18F25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F25K80-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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programmable buffer that is configured as a transmit
buffers are configured as receive buffers, FIFO will have
PIC18F66K80 FAMILY
27.4.3
In Mode 2, two or more receive buffers are used to form
the receive FIFO (first in, first out) buffer. There is no
one-to-one relationship between the receive buffer and
acceptance filter registers. Any filter that is enabled and
linked to any FIFO receive buffer can generate
acceptance and cause FIFO to be updated.
FIFO length is user-programmable, from 2-8 buffers
deep. FIFO length is determined by the very first
buffer. For example, if Buffer 2 (B2) is programmed as a
transmit buffer, FIFO consists of RXB0, RXB1, B0 and
B1, creating a FIFO length of 4. If all programmable
the maximum length of 8.
The following is the list of resources available in Mode 2:
• Three transmit buffers: TXB0, TXB1 and TXB2
• Two receive buffers: RXB0 and RXB1
• Six buffers programmable as TX or RX; receive
• Automatic RTR handling on B0-B5
• Sixteen acceptance filters: RXF0-RXF15
• Two dedicated acceptance mask registers;
• Programmable data filter on standard identifier
27.5
27.5.1
The PIC18F66K80 family devices implement three
dedicated transmit buffers – TXB0, TXB1 and TXB2.
Each of these buffers occupies 14 bytes of SRAM and
are mapped into the SFR memory map. These are the
only transmit buffers available in Mode 0. Mode 1 and
2 may access these and other additional buffers.
Each transmit buffer contains one Control register
(TXBnCON), four Identifier registers (TXBnSIDL,
TXBnSIDH, TXBnEIDL, TXBnEIDH), one Data Length
Count register (TXBnDLC) and eight Data Byte
registers (TXBnDm).
27.5.2
The PIC18F66K80 family devices implement two dedi-
cated receive buffers: RXB0 and RXB1. Each of these
buffers occupies 14 bytes of SRAM and are mapped
into SFR memory map. These are the only receive buf-
fers available in Mode 0. Mode 1 and 2 may access
these and other additional buffers.
DS39977C-page 444
buffers form FIFO: B0-B5
RXF15 programmable as third mask:
RXM0-RXM1, RXF15
messages: SDFLC, useful for DeviceNet protocol
CAN Message Buffers
MODE 2 – ENHANCED FIFO MODE
DEDICATED TRANSMIT BUFFERS
DEDICATED RECEIVE BUFFERS
Preliminary
Each receive buffer contains one Control register
(RXBnCON), four Identifier registers (RXBnSIDL,
RXBnSIDH, RXBnEIDL, RXBnEIDH), one Data Length
Count register (RXBnDLC) and eight Data Byte
registers (RXBnDm).
There is also a separate Message Assembly Buffer
(MAB) which acts as an additional receive buffer. MAB
is always committed to receiving the next message
from the bus and is not directly accessible to user firm-
ware. The MAB assembles all incoming messages one
by one. A message is transferred to appropriate
receive buffers only if the corresponding acceptance
filter criteria is met.
27.5.3
The ECAN module implements six new buffers: B0-B5.
These buffers are individually programmable as either
transmit or receive buffers. These buffers are available
only in Mode 1 and 2. As with dedicated transmit and
receive buffers, each of these programmable buffers
occupies 14 bytes of SRAM and are mapped into SFR
memory map.
Each buffer contains one Control register (BnCON),
four Identifier registers (BnSIDL, BnSIDH, BnEIDL,
BnEIDH), one Data Length Count register (BnDLC)
and eight Data Byte registers (BnDm). Each of these
registers contains two sets of control bits. Depending
on whether the buffer is configured as transmit or
receive, one would use the corresponding control bit
set. By default, all buffers are configured as receive
buffers. Each buffer can be individually configured as a
transmit or receive buffer by setting the corresponding
TXENn bit in the BSEL0 register.
When configured as transmit buffers, user firmware
may access transmit buffers in any order similar to
accessing dedicated transmit buffers. In receive
configuration with Mode 1 enabled, user firmware may
also access receive buffers in any order required. But
in Mode 2, all receive buffers are combined to form a
single FIFO. Actual FIFO length is programmable by
user firmware. Access to FIFO must be done through
the FIFO Pointer bits (FP<4:0>) in the CANCON
register. It must be noted that there is no hardware
protection against out of order FIFO reads.
PROGRAMMABLE TRANSMIT/
RECEIVE BUFFERS
2011 Microchip Technology Inc.
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