SI5110-H-BL Silicon Laboratories Inc, SI5110-H-BL Datasheet - Page 27

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SI5110-H-BL

Manufacturer Part Number
SI5110-H-BL
Description
IC TXRX SONET/SDH LP HS 99-PBGA
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI5110-H-BL

Product
PHY
Supply Voltage (max)
1.89 V, 3.47 V
Supply Voltage (min)
1.71 V
Supply Current
0.7 A
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 20 C
Mounting Style
SMD/SMT
Maximum Power Dissipation
1300 mW
Number Of Channels
1
Package / Case
BGA-99
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI5110-H-BL
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
A6, B6, C5,
Number(s)
G3, J3–4,
Pin
E3
K2
B5
B8
B7
F3
J7
RXAMPMON
RSVD_GND
RXCLK1+,
REFRATE
RXCLK1–
REFSEL
RESET
Name
I/O
O
O
I
I
I
Signal Level
Analog
LVTTL
LVTTL
LVTTL
LVDS
Rev. 1.4
Reference Clock Rate Select.
The REFRATE input sets the frequency for the
REFCLK input. When REFRATE is set high, the
REFCLK frequency is 1/16th the serial data rate
(nominally 155 MHz). When REFRATE is set low, the
REFCLK frequency is 1/32nd the serial data rate
(nominally 78 MHz).
The REFRATE input has no effect when the REFSEL
input is set low.
Note: This input has an internal pullup.
Reference Clock Selection.
This input selects the reference clock source to be
used by the Si5110 transmitter and receiver. The ref-
erence clock sets the operating frequency of the
Si5110 transmit CMU, which is used to generate the
high-speed transmit clock TXCLKOUT. The reference
clock is also used by the Si5110 receiver CDR to cen-
ter the PLL during lock acquisition, and as a reference
for determination of the receiver lock status.
When REFSEL = 0, the low-speed data input clock,
TXCLK4IN, is used as the reference clock. When
REFSEL = 1, the reference clock provided on
REFCLK is used.
Note: This input has an internal pullup.
Device Reset.
Forcing this input low for at least 1 μ s causes a device
reset. For normal operation, this pin should be held
high.
Note: This input has an internal pullup.
Reserved Tie To Ground.
Must be connected directly to GND for proper
operation.
Receiver Amplitude Monitor.
The RXAMPMON output provides an analog output
signal that is proportional to the input signal
amplitude. See Equation 1 for the relationship
between RXAMPON and RXDIN. This signal is active
when SLICEMODE is asserted.
Differential Receiver Clock Output 1.
The clock recovered from the signal present on
RXDIN is divided down to the parallel output word rate
and output on RXCLK1. In the absence of data, a sta-
ble clock on RXCLK1 can be maintained by asserting
LTR.
Description
Si5110
27

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