IDT70V3319S133BF IDT, Integrated Device Technology Inc, IDT70V3319S133BF Datasheet - Page 14

• Manufacturer Part Number: IDT70V3319S133BF
• Description: IC SRAM 4MBIT 133MHZ 208FBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70V3319S133BF

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 4M (256K x 18)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 70V3319S133BF

Timing Waveform of Left Port Write to Pipelined Right Port Read
NOTES:
1. CE
2. OE = V
3. If t
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read
NOTES:
1. CE
2. OE = V
3. If t
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
ADDRESS
ADDRESS
t
will be t
t
be t
CO
CO
ADDRESS
ADDRESS
DATA
DATA
DATA
CO
CO
0
0
CO
, UB, LB, and ADS = V
+ 2 t
DATA
, UB, LB, and ADS = V
+ t
CLK
CLK
R/W
R/W
< minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
< minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
OUT"B"
CYC
+ t
IL
CLK
R/W
CLK
R/W
IL
CO
OUT "B"
IN"A"
CYC2
for Port "B", which is being read from. OE = V
for the Right Port, which is being read from. OE = V
CD1
"A"
"A"
"A"
"B"
"B"
"B"
IN "A"
+ t
+ t
"A"
"A"
"A"
"B"
"B"
"B"
).
CYC2
CD1
+ t
CD2
). If t
+ t
). If t
CD2
CO
CO
).
> minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
t
MATCH
t
t
VALID
SW
SD
SA
IL
IL
> minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
; CE
; CE
t
MATCH
t
MATCH
SW
t
t
VALID
SA
t
SA
SD
SW
t
t
t
HD
HW
HA
1
1
, CNTEN, and REPEAT = V
, CNTEN, and REPEAT = V
MATCH
t
t
SA
t
t
SW
HW
HA
t
t
t
HA
HD
HW
t
DC
t
t
CO
t
HW
HA
(3)
t
CO
(3)
t
IH
CD1
for Port "A", which is being written to.
IH
IH
IH
.
.
for the Left Port, which is being written to.
MATCH
NO
6.42
14
t
CD2
VALID
MATCH
NO
MATCH
NO
Industrial and Commercial Temperature Ranges
VALID
MATCH
t
DC
NO
t
CD1
(1,2,4)
t
DC
VALID
5623 drw 10
5623 drw 11
(1,2,4)