SI3480-A01-GM Silicon Laboratories Inc, SI3480-A01-GM Datasheet - Page 11

• Manufacturer Part Number: SI3480-A01-GM
• Description: IC CTLR 4/8-PORT POE 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3480-A01-GM

• Applications: Power Over Ethernet Controller
• Current - Supply: 13mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN Exposed Pad
• Product: Power Distribution
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8. Landing Pattern: 20-Pin QFN
Figure 3 illustrates the landing pattern for the Si3480. Table 8 lists the values for the dimensions shown in the
illustration.
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
Dimension
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 2x2 array of 0.95mm openings on a 1.1 mm pitch should be used for the center pad to
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
C1
C2
X1
E
mask and the metal pad is to be 60 m minimum, all the way around the pad.
to assure good solder paste release.
assure the proper paste volume (71% Paste Coverage).
Body Components.
Figure 3. QFN-20 Recommended PCB Land Pattern
Table 8. QFN-20 PCB Land Pattern Dimensions
0.20
Min
3.70
3.70
0.50
Max
0.30
Rev. 1.0
Dimension
X2
Y1
Y2
2.15
0.90
2.15
Min
2.25
Max
2.25
1.00
Si3480
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