AS1372-BWLT-15 austriamicrosystems, AS1372-BWLT-15 Datasheet - Page 10

• Manufacturer Part Number: AS1372-BWLT-15
• Description: IC REG LDO 350MA 1.5V 5WLCSP
• Manufacturer: austriamicrosystems

Specifications of AS1372-BWLT-15

• Regulator Topology: Positive Fixed
• Voltage - Output: 1.5V
• Voltage - Input: Up to 4.5V
• Voltage - Dropout (typical): 0.135V @ 350mA
• Number Of Regulators: 1
• Current - Output: 350mA (Min)
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 5-UFBGA, WLCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -
• Other names: AS1372-BWLT-15TR

AS1372
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
9 Application Information
Advantages of dual supply architecture vs. traditional single supply approach.
If compared to the traditional single supply approach, the dual rail architecture ensures improved performances in a
LDO at the expense of an additional supply voltage and a dedicated pin.
Anyhow, it is worth to note that the additional supply voltage comes for free in all those applications where the LDO is
supplied by the output of a DCDC step-down converter: Vin pin is coupled to the step-down output and Vbias is
shorted to the DCDC converter supply.
Figure 20. Single vs. Dual Supply
Single Supply
Dual Supply
V
V
BIAS
IN
V
IN
Bandgap
Bandgap
-
+
NMOS
PMOS
V
-
+
OUT
V
error
error
OUT
core
core
amplifier
amplifier
blocks
blocks
The former is based on a PMOS output transistor connected in a common source configuration: the supply voltage at
its source is shared with all the circuit. On the other side, the dual supply approach is based on a NMOS transistor in
common drain configuration having its source coincident with the regulated output of the LDO: the supply voltage at
the drain is not shared with the remaining blocks of the circuit and its value can be chosen independently.
The second solution allows improved efficiency and dropout at low output reference voltage and faster transient time
response.
Improved efficiency
At heavy current load the power consumption is almost entirely located in the output transistor. This means that
keeping drain to source voltage, that is the difference between input and output voltage of the LDO, as small as
possible is the key factor for a good efficiency. It holds, approximately: Efficiency = (Vout / Vin)x100 [%]
While this achievement is little challenging in case the output voltage is large enough, traditional implementations
based on a PMOS device face a serious bottleneck at low output voltage. In fact the supply voltage cannot be made
consequently small because of dynamic range limitations in the core of the LDO circuitry. In many commercial cases
the supply voltage cannot be made smaller than 2 or 2,5V which gives only 25% or 20% efficiency for a 500mV
reference output.
On the contrary, the possibility to have a dedicated supply voltage for the output transistor offers the possibility to set
the drain to source voltage of the output transistor independently from the dynamic range limitations inside the core of
the circuit. Thus, even at very small output voltage, the drain to source voltage can be made quite small and guarantee
optimal efficiency performance. For instance, by setting Vin at 800mV makes more than 60% efficiency for an output
voltage as small as 500mV still ensuring excellent analog performances in the LDO.
www.austriamicrosystems.com/LDOs/AS1372
Revision 1.01
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