IR3473MTRPBF International Rectifier, IR3473MTRPBF Datasheet - Page 12

• Manufacturer Part Number: IR3473MTRPBF
• Description: IC BUCK SYNC ADJ 6A PQFN
• Manufacturer: International Rectifier
• Series: SupIRBuck™r
• Type: Step-Down (Buck), PWM - Current Moder

Specifications of IR3473MTRPBF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.5 V ~ 12 V
• Current - Output: 6A
• Frequency - Switching: Up to 750kHz
• Voltage - Input: 3 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Primary Input Voltage: 27V
• No. Of Outputs: 1
• Output Voltage: 12V
• Output Current: 6A
• No. Of Pins: 17
• Operating Temperature Range: -40°C To +125°C
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Part Status: Preferred
• Package: PQFN / 4 x 5
• Circuit: Single Output
• Iout (a): 6
• Switch Freq (khz): 0 - 750
• Input Range (v): 3.0 - 27
• Output Range (v): 0.5 - 12
• Ocp Otp Uvlo Pre-bias Soft Start And: Constant On-Time + PGOOD + EN + Temp Comp OCP
• Digital Home Media: Yes
• Mobile Computing: Yes
• Industrial 24v Input: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
PWM COMPARATOR
The PWM comparator initiates a SET signal (PWM pulse)
when the FB pin falls below the reference (VREF) or the
soft start (SS) voltage.
ON‐TIME GENERATOR
The PWM on‐time duration is programmed with an
external resistor (R
pin. The simplified equation for R
The FF pin is held to an internal reference after EN goes
HIGH. A copy of the current in R
capacitor, which sets the on‐time duration, as shown in
equation 2.
CONTROL LOGIC
The control logic monitors input power sources, sequences
the converter through the soft‐start and protective modes,
and initiates an internal RUN signal when all conditions are
met.
VCC and 3VCBP pins are continuously monitored, and the
IR3473 will be disabled if the voltage of either pin drops
below the falling thresholds. EN_DELAY will become HIGH
when VCC and 3VCBP are in the normal operating range
and the EN pin = HIGH.
SOFT START
With EN = HIGH, an internal 10µA current source charges
the external capacitor (C
voltage slew rate during the soft start interval. The soft
start time (t
The feedback voltage tracks the SS pin until SS reaches the
0.5V reference voltage (Vref), then feedback is regulated
to Vref. C
SS
will continue to be charged, and when SS pin
SS
T
12
R
) can be calculated from equation 3.
ON
FF
t


SS
FF
February 16, 2011 | ADVANCED DATASHEET | V1.9 | PD97601
1
) from the input supply (VIN) to the FF
R
V

FF

C
20

SS
1
V
) on the SS pin to set the output
SS
10
V 
V
OUT
pF
IN


20
0
A
5 .

FF
F
FF
charges a timing
pF
V
SW
is shown in equation 1.
(3)
(2)
(1)
6A Highly Integrated SupIRBuck
reaches V
HIGH. With EN_DELAY = LOW, the capacitor voltage and SS
pin is held to the FB pin voltage. A normal startup
sequence is shown in Figure 23.
PGOOD
The PGOOD pin is open drain and it needs to be externally
pulled high. High state indicates that output is in
regulation. The PGOOD logic monitors EN_DELAY,
SS_DELAY, and under/over voltage fault signals. PGOOD is
released only when EN_DELAY and SS_DELAY = HIGH and
output voltage is within the OV and UV thresholds.
PRE‐BIAS STARTUP
IR3473 is able to start up into pre‐charged output, which
prevents oscillation and disturbances of the output
voltage.
With constant on‐time control, the output voltage is
compared with the soft start voltage (SS) or Vref,
depending on which one is lower, and will not start
switching unless the output voltage drops below the
reference. This scheme prevents discharge of a pre‐biased
output voltage.
SHUTDOWN
The IR3473 will shutdown if VCC is below its UVLO limit.
The IR3473 can be shutdown by pulling the EN pin below
its lower threshold. Alternatively, the output can be
shutdown by pulling the soft start pin below 0.3V.
SS
(see Electrical Specification), SS_DELAY goes
Figure 23: Normal Startup
TM
IR3473