IR3865MTRPBF International Rectifier, IR3865MTRPBF Datasheet
IR3865MTRPBF
Specifications of IR3865MTRPBF
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IR3865MTRPBF Summary of contents
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SupIRBuck TM WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR Features Input Voltage Range 21V Output Voltage Range: 0.5V to 12V Continuous 10A Load Capability Constant On-Time Control Compensation Loop not Required Excellent Efficiency at ...
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... These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PACKAGE INFORMATION 4mm x 5mm POWER QFN ORDERING INFORMATION PKG DESIG M M 2/16/2011 Rev2.3 PACKAGE PIN COUNT DESCRIPTION IR3865MTRPbF 17 IR3865TR1PbF 17 IR3865MBF ...
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Simplified Block Diagram 2/16/2011 Rev2.3 IR3865MBF 3 ...
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Pin Description I/O NAME NUMBER LEVEL FCCM 1 3.3V ISET 2 PGOOD 3 5V GND 4,17 Reference 3.3V 3VCBP 8 3. VCC 10 5V PGND 11 Reference PHASE 12 ...
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Recommended Operating Conditions Symbol Definition VIN Input Voltage VCC Supply Voltage V Output Voltage OUT I Output Current OUT Fs Switching Frequency T Junction Temperature J * Note: PHASE pin must not exceed 25V. Electrical Specifications Unless otherwise specified, these ...
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Electrical Specifications (continued) Unless otherwise specified, these specification apply over VIN = 12V, 4.5V<VCC<5.5V, 0 PARAMETER GATE DRIVE Deadtime BOOTSTRAP PFET Forward Voltage UPPER MOSFET Static Drain-to-Source On- Resistance LOWER MOSFET Static Drain-to-Source On- Resistance FAULT PROTECTION ISET Pin Output ...
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TYPICAL OPERATING DATA Tested with demoboard shown in Figure 7, VIN = 12V, VCC = 5V, VOUT = 1.05V 300kHz, T airflow, unless otherwise specified 95% 90% 85% 80% 75% 7VIN 70% 12VIN 65% 16VIN 60% 55% 50% ...
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TYPICAL APPLICATION CIRCUIT +3.3V VCC R1 10K R2 10K EN TP4 EN FCCM SW1 EN / FCCM R4 8.66K VSW ISET +3. 10K 2 PGOOD 3 TP11 PGOOD TP13 SS 7 C20 0.1uF ...
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TYPICAL OPERATING DATA Tested with demoboard shown in Figure 7, VIN = 12V, VCC = 5V, VOUT = 1.05V 300kHz, T airflow, unless otherwise specified EN PGOOD SS VOUT 5V/div 5V/div 1V/div 500mV/div Figure 8: Startup VOUT PHASE ...
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TYPICAL OPERATING DATA Tested with demoboard shown in Figure 7, VIN = 12V, VCC = 5V, VOUT = 1.05V 300kHz, T airflow, unless otherwise specified VOUT PHASE i L 50mV/div 5V/div 2A/div Figure 14: Load Transient 0-4A FCCM ...
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CIRCUIT DESCRIPTION PWM COMPARATOR The PWM comparator initiates a SET signal (PWM pulse) when the FB pin falls below the reference (VREF) or the soft start (SS) voltage. ON-TIME GENERATOR The PWM on-time duration is programmed with an external resistor ...
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CIRCUIT DESCRIPTION UNDER/OVER VOLTAGE MONITOR The IR3865 monitors the voltage at the FB node through a 350ns filter. If the FB voltage is below the under voltage threshold, UV# is set to LOW holding PGOOD to be LOW. If the ...
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CIRCUIT DESCRIPTION GATE DRIVE LOGIC The gate drive logic features adaptive dead time, diode emulation, and a minimum lower gate interval. An adaptive dead time simultaneous conduction of the upper and lower MOSFETs. The lower gate voltage must be below ...
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COMPONENT SELECTION Input Capacitor Selection The main function of the input capacitor bank is to provide the input ripple current and fast slew rate current during the load current step up. The input capacitor bank must have adequate ripple current ...
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COMPONENT SELECTION The output voltage drop, depends on the characteristic of the output capacitor the sum of the equivalent DROP series inductance (ESL) of the output capacitor times the rate of change of the output current and the ...
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DESIGN EXAMPLE Design Criteria: Input Voltage, VIN = 7V to 16V Output Voltage, VOUT = 1.5V Switching Frequency 300kHz Inductor Ripple Current, 2Δ Maximum Output Current, IOUT = 10A Over Current Trip, IOC = 15A Overshoot ...
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STABILITY CONSIDERATIONS Constant-on-time control is a fast , ripple based control scheme. Unstable operation can occur if certain conditions are not met. The system instability is usually caused by: • Switching noise coupled to FB input: This causes the PWM ...
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PCB Metal and Components Placement Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to ...
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Solder Resist It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should ...
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Stencil Design The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on ...
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IR WORLD HEADQUARTERS: 2/16/2011 Rev2.3 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/11 IR3865MBF TAC Fax: (310) 252-7903 21 ...