IP1837TRPBF International Rectifier, IP1837TRPBF Datasheet - Page 19

• Manufacturer Part Number: IP1837TRPBF
• Description: IC DC-DC REG SYNC BUCK LGA
• Manufacturer: International Rectifier
• Series: iPOWIR™r
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of IP1837TRPBF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.6 V ~ 12 V
• Current - Output: 35A
• Frequency - Switching: 250kHz ~ 1.5MHz
• Voltage - Input: 1.5 V ~ 16 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Package: LGA - 7.7 x 7.7
• Circuit: Single Output
• Iout (a): 35
• Switch Freq (khz): 250 - 1500
• Input Range (v): 1.5 - 16
• Output Range (v): 0.6 - 0.75*Vin
• Internal Bias Ldo: Yes
• Ocp Otp Uvlo Pre-bias Soft Start And: Remote Sense + Body Tracking + Temp Comp OCP
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MINIMUM ON TIME CONSIDERATIONS
The minimum ON time is the shortest amount of time for
which the Control FET may be reliably turned on, and this
depends on the internal timing delays. For the iP1837,
the minimum on‐time is specified as 50 ns maximum.
Any design or application using the iP1837 must require a
pulse width that is at least equal to this minimum on‐time
and preferably higher than 100 ns. This is necessary for the
circuit to operate without jitter and pulse‐skipping, which
can cause high inductor current ripple and high output
voltage ripple.
MAXIMUM DUTY RATIO CONSIDERATIONS
For the iP1837, the upper limit on the operating duty ratio
is set by the duration of the PWMSet pulse or by the 200
ns fixed off‐time, whichever is higher. Since the PWMSet
pulse has a 25% duty cycle, this limits the maximum duty
ratio at which the iP1837 can operate, to 75%. At switching
frequencies above 1.25 MHz, however, the maximum duty
ratio is set by the 200 ns fixed off‐time. Thus, at switching
frequencies above 1.25 MHz, higher the switching
frequency, the lower is the maximum duty ratio at which
the iP1837 can operate. Figure 13 shows a plot of the
maximum duty ratio v/s the switching frequency, with 200
ns off‐time.
Figure 13: Maximum duty cycle v/s switching frequency.
76%
75%
74%
73%
72%
71%
70%
69%
68%
67%
66%
250
350 450
19
550 650
March 3, 2011 | V1.24
750
Switching Frequency (kHz)
850
950 1050 1150 1250 1350 1450 1550 1650
Highly Integrated 35A Single‐input Voltage,
Synchronous Buck Regulator
TRAILING EDGE PULSE WIDTH MODULATION
WITH RAMP‐SLOPE MODULATION
The iP1837 employs trailing edge Pulse width modulation.
However, unlike conventional trailing edge modulators,
which compare the PWM ramp with the output of the
error amplifier or the Comp voltage, in the modulation
scheme used in the iP1837, the slope of the PWM ramp
is modulated by the Comp voltage and this modulated
ramp is then compared to a fixed reference voltage.
The advantage of this scheme is that comparison always
takes place at a fixed reference irrespective of the duty
cycle of operation. Conventional modulators suffer from
increased noise susceptibility at the lower duty cycles,
since the comparison takes place at the Comp voltage level
which is close to the bottom of the PWM ramp for low
duty cycle operation.
Figure 14 shows theoretical waveforms for the PWM ramp
and the PWM output in response to a changing Comp
voltage. Figure 15 shows the variation of the modulator
gain (F
Figure 14: Theoretical waveforms for the new PWM scheme
1.4
1.2
0.8
0.6
0.4
0.2
1
0
5
Figure 15: Modulator gain (F
m
) with the duty cycle (D).
10
15
Modulator Gain = -2E-05D
20
25
D(%)
30
m
2
) v/s Duty Ratio (D%)
+ 0.0156D + 0.4168
35
40
iP1837
45
50
97600
55