IP1206TRPBF International Rectifier, IP1206TRPBF Datasheet - Page 23

• Manufacturer Part Number: IP1206TRPBF
• Description: IC PWR BLOCK MULTIPHASE 30A LGA
• Manufacturer: International Rectifier
• Series: iPOWIR™r
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of IP1206TRPBF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1 or 2
• Voltage - Output: 0.8 V ~ 5.5 V
• Current - Output: 30A, 15A
• Frequency - Switching: 200kHz ~ 600kHz
• Voltage - Input: 7.5 V ~ 14.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Package: LGA - 15.5 x 9.25
• Circuit: Single Output or Dual Ch
• Iout (a): 30
• Switch Freq (khz): 200 - 600
• Input Range (v): 7.5 - 14.5
• Output Range (v): 0.8 - 5.5
• Ocp Otp Uvlo Pre-bias Soft Start And: Pre-Bias + SEQ + SYNC + Tracking
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Fig. 23: The Compensation network for current loop
Compensation
(slave channel)
The
transconductance
configuration the main goal for the slave channel
feedback loop is to control the inductor current to
match the master channel inductor current as
well provides highest bandwidth and adequate
phase margin for overall stability. The following
analysis is valid for both using external current
sense resistors and using DCR of inductor.
The transfer function of power stage is
expressed by:
Where:
V
L
V
As shown the G(s) is a function of inductor
current. The transfer function for compensation
network is given by equation (21), when using a
series RC circuit as shown in Fig 23.
The loop gain function is:
2
in
osc
D
=Output inductor
=Input voltage
(
=Oscillator Peak Voltage
s
G
)
H
=
slave
(
s
(
V
s
)
R
e
)
=
(
s
=
s
2
)
I
R
H
L
=
V
s
R
2
R
2
( =
error
(
e
⎛
⎜ ⎜
⎝
s
S1
*
S2
s
g
)
⎛
⎜ ⎜
⎝
)
m
Fb2
g
I
I
=
L2
L1
*
m
[
G
Vp2
*
R
sL
R
(
amplifier,
R
R
s
s
for
s
amplifier
1
2
2
L
* )
V
L
1 s
s
⎞
⎟ ⎟
⎠
2
*
2
1
in
*
⎞
⎟ ⎟
⎠
V
D
*
⎛ +
⎜ ⎜
⎝
E/A2
osc
(
1
⎛ +
⎜ ⎜
⎝
s
1
* )
Current
sC
sC
R
sC
sR
s
2
2
- -
2
Comp2
2
R
is
2
]
C
in
2
- -
2
⎞
⎟ ⎟
⎠
⎞
⎟ ⎟
⎠
R
(
C
*
differentia l
20
2
⎛
⎜ ⎜
⎝
2
2-phase
sL
- -
Ve
)
Loop
2
- -
V
*
in
V
(
21
osc
2/26/2008
⎞
⎟ ⎟
⎠
)
H
Select a zero frequency for current loop (F
times larger than zero cross frequency for
voltage loop (F
From (22), R2 can be expressed as:
V
V
g
L
R
F
This results to : R
The power stage of current loop has a dominant
pole (Fp) at frequency expressed by:
Where Rds(on1) is the on-resistance of control
FET, Rds(on2) is the on-resistance of
synchronous FET, RL is the DCR of output
inductance and D is the duty cycle
Req=9.48mOhm
Set the zero of compensator at 10 times the
dominant pole frequency FP, the compensator
capacitor, C2 can be expressed as:
C2=1nF
All designs should be tested for stability to verify
the calculated values.
m
2
o2
(
in
osc
s1
=1uH
F
=2800umoh
=12V
=60kHz
=DCR=2.4mOhm
R
O
=1.25V
2
eq
R
)
=
2
=
=
R
g
ds
m
g
(
*
on
m
R
1
R
F
1
*
)
F
eq
O
*
s
C
F
1
R
o1
2
P
D
z
=
*
2
s
≅
=
).
1
=
=
R
+
R
2
1
*
2
10
=5.84K
2
.
ds
R
2
π
5
2
*
R
(
π
ds
on
%
π
*
*
eq
2
(
)
on
*
L
F
π
*
+
*
R
2
2
P
1
F
)
F
*
R
iP1206PbF
2
( *
O
O
F
L
1
*
2
V
1
O
+
F
*
2
in
V
−
z
R
*
L
in
D
s
2
L
)
*
2
+
*
V
R
V
osc
L
osc
=
1
- -
o2
- -
) 1.5
- -
(
23
- -
23
(
)
22
)