HV9985K6-G Supertex, HV9985K6-G Datasheet - Page 10
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HV9985K6-G
Manufacturer Part Number
HV9985K6-G
Description
LED Drivers Three Channel Closed Loop LED Driver
Manufacturer
Supertex
Datasheet
1.HV9985K6-G.pdf
(16 pages)
Specifications of HV9985K6-G
Operating Supply Voltage
10 V to 40 V
Package / Case
QFN-40
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HV9985K6-G
Manufacturer:
FUJITSU
Quantity:
124
If the short circuit occurs when the PWM dimming signal is
already high, the time to detect will be:
Over Voltage Protection
The HV9985 provides hysteretic over voltage protection,
allowing the IC to recover in case the LED load is discon-
nected momentarily.
When the load is disconnected in a boost converter, the
output voltage rises as the output capacitor starts charging.
When the output voltage reaches the OVP rising threshold,
the HV9985 detects an over voltage condition and turns off
the converter. The converter is turned back on only when the
output voltage falls below the falling OVP threshold (which
is 10% lower than the rising threshold). This time is mostly
dictated by the R-C time constant of the output capacitor C
and the resistor network used to sense over voltage (R
+ R
cycle maintains the output voltage within a 10% band.
In most designs, the falling OVP threshold will be more than
the LED string voltage. Thus, when the LED load is recon-
nected to the output of the converter, the voltage differential
between the actual output voltage and the LED string volt-
age will cause a spike in the output current. This causes a
short circuit to be detected, and the short circuit protection in
the HV9985 will be triggered. This behavior continues until
the output voltage becomes lower than the LED string volt-
age. When this occurs, no fault will be detected, and normal
operation of the circuit will commence.
Note:
The overvoltage thresholds for the three channels in the
HV9985 are derived by using resistor dividers from the re-
spective VDDs. The resistor dividers are adjusted to give
a 1.25V OVP rising trip point and a 1.125V OVP falling
trip point at V
in the electrical characteristics table of the datasheet as-
sume a V
the HV9985. Using an external voltage source at VDD will
change the OVP trip points proportionally.
OVP2
t
DETECT1
). In case of a persistent open circuit condition, this
= t
DD
DELAY
voltage generated by the linear regulator of
DD
≈ 200ns(max)
= 5.0V. The OVP trip points mentioned
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
OVP1
O
10
Layout Considerations
For multi-channel peak current mode controller IC to work
properly with minimum interference between the channels,
it is important to have a good PCB layout which minimizes
noise. Following the layout rules stated below will help to
ensure proper performance of all three channels.
1. GND Connection
2. VDD Connection
3. REF Connection
4. GATE and CS connection
5. OVP protection
The IC has four separate ground connections - one for
each of the three channels and one analog ground for
the common circuitry. It is recommended that four sepa-
rate ground planes be used in the PCB, and all the GND
planes be connected together at the return terminal of
the input power lines.
Each VDD pin should be bypassed with a low ESR ca-
pacitor to its OWN ground (i.e. VDD1 is bypassed to
GND1 and so on). The common VDD pin can be by-
passed to the common GND.
In case all the references are going to be driven from a
single voltage source, it is recommended to have a small
R-C low pass filter (1.0k, 1.0nF) at each REF pin with
the filter being referenced to the appropriate channel’s
ground (as in the case of the VDD pins). If the REF pins
are driven with three individual voltage sources, then
just a small capacitor (1.0nF) at each pin would suffice.
The connection from GATE output to the gate of the ex-
ternal FET as well as the connection from the CS pin to
the external sense resistor made as short as possible to
avoid false trigerrings.
Typically, the OVP resistor dividers would be located
away from the IC. To prevent false trigerrings of the IC
due to noise at the OVP pin, a small bypass capacitor
(1.0nF) right at the OVP pin is recommended.
●
Tel: 408-222-8888
●
www.supertex.com
HV9985