NCP1587EDR2G ON Semiconductor, NCP1587EDR2G Datasheet

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... Pb−Free Device PIN CONNECTIONS BST GND (Top View) ORDERING INFORMATION Device Package NCP1587EDR2G SOIC−8 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1 MARKING DIAGRAM 8 1587E ALYW G 1 ...

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0 REF COMP/DIS 3 BST FB COMP/DIS TG PHASE BG GND Figure 1. Typical Application Diagram POR UVLO FAULT LATCH FAULT + R PWM - Q ...

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PIN FUNCTION DESCRIPTION Pin No. Symbol 1 BST Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to BST pin). Connect ...

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ELECTRICAL CHARACTERISTICS (−40_C < < PHASE < 1.0 nF, for min/max values unless otherwise noted Characteristic Input Voltage Range Boost Voltage Range Supply Current Quiescent Supply Current V ...

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TYPICAL CHARACTERISTICS 5.0 4.7 4.4 4.1 3.8 3 JUNCTION TEMPERATURE (°C) J Figure 3. I vs. Temperature JUNCTION ...

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General The NCP1587E is a PWM controller intended for DC−DC conversion from 5.0 V & buses. The device has internal gate driver circuit designed to drive N−channel MOSFETs in a synchronous−rectifier buck topology. The output ...

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UVLO Undervoltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when V support the internal rails and power the converter. For the NCP1587E, the UVLO is set to permit operation when converting from a 5.0 input ...

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Input Capacitor Selection The input capacitor has to sustain the ripple current produced during the on time of the upper MOSFET must have a low ESR to minimize the losses. The RMS value of this ripple is: Iin ...

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In contrast, smaller values of inductance increase the regulator’s maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. The peak-to-peak ripple current for NCP1587E is given by the following ...

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P = control IC power dissipation measured supply current supply voltage top gate driver losses bottom gate driver losses. BG The upper (switching) MOSFET gate driver ...

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Figure 13. Closed-loop Voltage Loop-gain of the NCP1587E DESIGN EXAMPLE II: Type III Compensation (Oscon Cap. with small ESR; Do not place R Switching Frequency F Output Capacitance R Output Capacitance C Output Inductance L Input Voltage V Output Voltage ...

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After choose R4 value, adjust R4 to get enough phase margin Ù 665 W 2nd pole; Choose C to eliminate the noise 275 KHz ...

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VCC GND 5 3 Figure 15. Demo Board PCB Layout http://onsemi.com 13 ...

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... TP U1 NCP1587E http://onsemi.com 14 Quantity MFG 1 PANASONIC TAIYO YUDEN 1 AVX 2 PANASONIC PANASONIC TDK 1 ON SEMICONDUCTOR 1 PANASONIC 1 MOLEX 1 PASTERNACK ENTERPRISES 1 PANASONIC SEMICONDUCTOR 2 ON SEMICONDUCTOR 2 ON SEMICONDUCTOR 2 ON SEMICONDUCTOR SEMICONDUCTOR 1 PANASONIC 2 DALE DALE 3 PANASONIC DALE 24 DALE 24 PANASONIC 1 DALE 1 DALE 16 KEYSTONE 1 ON SEMICONDUCTOR ...

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Figure 16. Gate Waveforms 20 A Load Sustaining Figure 18. Start-up Sequence Figure 17. Over Current Protection (12 Trip) Figure ...

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... *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “ ...