EVAL-ADF4001EBZ2 Analog Devices Inc, EVAL-ADF4001EBZ2 Datasheet - Page 4
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EVAL-ADF4001EBZ2
Manufacturer Part Number
EVAL-ADF4001EBZ2
Description
BOARD EVAL FOR ADF4001
Manufacturer
Analog Devices Inc
Datasheet
1.ADF4001BRUZ.pdf
(16 pages)
Specifications of EVAL-ADF4001EBZ2
Main Purpose
Timing, Clock Generator
Embedded
No
Utilized Ic / Part
ADF4001
Primary Attributes
1 Input, 1 Output
Secondary Attributes
2.7 V ~ 5.5 V Supply
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADF4001
TSSOP
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LFCSP
Pin No.
19
20
1
2, 3
4
5
6, 7
8
9, 10
11
12
13
14
15
16, 17
18
Mnemonic
R
CP
CPGND
AGND
RF
RF
AV
REF
DGND
CE
CLK
DATA
LE
MUXOUT
DV
V
CPGND
AGND
RF
RF
REF
SET
P
AV
R
IN
IN
SET
DD
IN
IN
CP
DD
DD
IN
B
A
IN
B
A
1
2
3
4
5
6
7
8
(Not to Scale)
ADF4001
TSSOP
TOP VIEW
Function
Connecting a resistor between this pin and CPGND sets the maximum charge pump
output current. The nominal voltage potential at the R
between I
So, with R
Charge Pump Output. When enabled, this provides ± I
in turn, drives the external VCO or VCXO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the N counter. This point must be decoupled to the ground
plane with a small bypass capacitor, typically 100 pF. See Figure 3.
Input to the N counter. This small signal input is ac-coupled to the external VCO or VCXO.
Analog Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AV
same value as DV
Reference Input. This is a CMOS input with a nominal threshold of V
equivalent input resistance of 100 kΩ. See Figure 2. This input can be driven from a TTL
or CMOS crystal oscillator or can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump
output into three-state mode. Taking the pin high will power up the device, depending on
the status of the power-down bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The
data is latched into the 24-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control
bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is
loaded into one of the four latches, the latch being selected by using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
Digital Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
digital ground plane should be placed as close as possible to this pin. DV
same value as AV
Charge Pump Power Supply. This should be greater than or equal to V
where V
range of up to 5 V.
16
15
14
13
12
11
10
9
NOTE: TRANSISTOR COUNT 6425 (CMOS) AND 50 (BIPOLAR)
DV
MUXOUT
LE
DATA
CLK
CE
DGND
V
P
DD
PIN FUNCTION DESCRIPTIONS
DD
CP
SET
is 3 V, it can be set to 5 V and used to drive a VCO or VCXO with a tuning
PIN CONFIGURATIONS
and R
= 4.7 kΩ, I
DD
DD.
I
SET
CP
.
M
is
AX
–4–
CP MAX
=
R
23 5 .
SET
= 5 mA.
CPGND 1
AGND 2
AGND 3
RF
RF
IN
IN
B 4
A 5
ADF4001
TOP VIEW
LFCSP
PIN 1
INDICATOR
SET
CP
to the external loop filter which,
pin is 0.66 V. The relationship
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
DD
DD
DD
DD
/2 and a dc
. In systems
must have the
must be the
REV. A