SERDESUR-65USB/NOPB National Semiconductor, SERDESUR-65USB/NOPB Datasheet - Page 33
SERDESUR-65USB/NOPB
Manufacturer Part Number
SERDESUR-65USB/NOPB
Description
EVAL BOARD FOR DS90UR905
Manufacturer
National Semiconductor
Datasheet
1.DS90UR905QSQENOPB.pdf
(44 pages)
Specifications of SERDESUR-65USB/NOPB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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FIGURE 28. BIST Mode Flow Diagram
30102043
FIGURE 29. BIST Waveforms
33
BER Calculations
It is possible to calculate the approximate Bit Error Rate
(BER). The following is required:
•
•
•
The BER is less than or equal to one over the product of 24
times the PCLK rate times the test duration. If we assume a
65MHz PCLK, a 10 minute (600 second) test, and a PASS,
the BERT is
The BIST mode runs a check on the data payload bits. The
LOCK pin also provides a link status. It the recovery of the C0
and C1 bits does not reconstruct the expected clock signal,
the LOCK pin will switch Low. The combination of the LOCK
and At-Speed BIST PASS pin provides a powerful tool for
system evaluation and performance monitoring.
Pixel Clock Frequency (MHz)
BIST Duration (seconds)
BIST test Result (PASS)
≤
1.07 X 10E-12
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30102064
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