DS90UR908Q-EVK/NOPB National Semiconductor, DS90UR908Q-EVK/NOPB Datasheet - Page 3

• Manufacturer Part Number: DS90UR908Q-EVK/NOPB
• Description: EVAL BOARD FOR DS90UR908Q
• Manufacturer: National Semiconductor

Specifications of DS90UR908Q-EVK/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Name
LVCMOS Outputs
LOCK
Control and Configuration
PDB
VODSEL
OEN
OSS_SEL
LFMODE
MAPSEL
CONFIG[1:0]
SSC[2:0]
RES
Control and Configuration — STRAP PIN
For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP pin is read upon
power-up and set device configuration. Pin number listed along with shared LVCMOS Output name in square bracket.
EQ
Optional BIST Mode
BISTEN
PASS
Pin #
27
1
33
30
35
36
34
11,10
7, 2, 3
37
28 [PASS]
29
28
I/O, Type
O, LVMOS
I, LVCMOS
w/ pull-down
I, LVCMOS
w/ pull-down
I, LVCMOS
w/ pull-down
I, LVCMOS
w/ pull-down
I, LVCMOS
w/ pull-down
I, LVCMOS
w/ pull-down
I, LVCMOS
w/ pull-down
I, LVCMOS
w/ pull-down
I, LVCMOS
w/ pull-down
STRAP
I, LVCMOS
w/ pull-down
I, LVCMOS
w/ pull-down
O, LVCMOS PASS Output (BIST Mode) – Optional
Description
LOCK Status Output
LOCK = 1, PLL is locked, output states determined by OEN.
LOCK = 0, PLL is unlocked, output states determined by OSS_SEL and OEN.
May be used as a Link Status or to flag when the Video Data is active (ON/OFF).
Power Down Mode Input
PDB = 1, Device is enabled (normal operation)
PDB = 0, Device is in power-down, the outputs are TRI-STATE. Control registers are
RESET.
FPD-Link Output Voltage Select.
VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typ)
VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typ)
Output Enable Input
Table 3
Output Sleep State Select Input
See
Low Frequency Mode — Pin or Register Control
LF_MODE = 1, low frequency mode (TxCLKOUT = 5-20 MHz)
LF_MODE = 0, high frequency mode (TxCLKOUT = 20-65 MHz)
FPD-Link Map Select — Pin or Register Control
MAPSEL = 1, MSB on TxOUT3+/-,
MAPSEL = 0, LSB on TxOUT3+/-,
Operating Modes — Pin or Register Control
Determine the device operating mode and interfacing device.
CONFIG[1:0] = 00: Interfacing to DS90UR905Q or DS90UR907Q, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR905Q or DS90UR907Q, Control Signal Filter
ENABLED
CONFIG[1:0] = 01: Interfacing to DS90UR241 or DS99R421
CONFIG[1:0] = 11: Interfacing to DS90C241
Spread Spectrum Clock Generation (SSCG) Range Select
See Tables 5, 6
Reserved
Tie Low
EQ Gain Control of FPD-Link II Input
EQ = 1, EQ gain is enabled (~13 dB)
EQ = 0, EQ gain is disabled (~1.625 dB)
BIST Enable Input – Optional
BISTEN = 1, BIST Mode is enabled.
BISTEN = 0, normal mode.
PASS = 1, no errors detected
PASS = 0, errors detected
Leave open if unused. Route to a test point (pad) recommended.
Table
3.
3
Table 4
Figure 14
Figure 15
Table 1
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Table 3