CY3280-28XXX Cypress Semiconductor Corp, CY3280-28XXX Datasheet - Page 20

• Manufacturer Part Number: CY3280-28XXX
• Description: KIT DEV CAPSENSE CTLR UNIV
• Manufacturer: Cypress Semiconductor Corp
• Series: CapSense™r

Specifications of CY3280-28XXX

• Main Purpose: Interface, Sensor, CapSense® Touch
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CY8C28000
• Primary Attributes: Requires CY3280 Module Board
• Secondary Attributes: CD contains sample projects
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Hardware Design Notes
3.1.2
3.1.3
20
If you want more information about the LP3875ES-ADJ, refer to the part’s data sheet at
www.national.com/mpf/LP/LP3875-ADJ.html.
If the fixed 5V power supply is selected for the PSoC VCC, follow the steps below.
1. Unplug the external 12V power supply and 9V battery power.
2. Place shunts on pin 2 and pin 3 of JP3.
3. Plug in the external 12V power supply or 9V battery power.
If Vadj is selected for the PSoC power supply, follow the steps below.
1. Remove any shunts on JP3.
2. Plug in the external 12V power supply or 9V battery power.
3. Measure the voltage of pin 1 of JP3 with a multimeter, tuning the potentiometer RV1 until the
4. Unplug the external 12V power supply and 9V battery power.
5. Place shunts on pin 1 and pin 2 of JP3.
6. Plug in the external 12V power supply or 9V battery power.
Dual Channel CSD Scanning
The most significant improvement of CY8C28XXX over previous parts is the Dual-Channel CSD
scanning feature. Demonstrating this new feature requires two external capacitors. According to the
CY8C28xxx PSoC Programmable System-on-Chip Technical Reference Manual, pin 5 and pin 7 of
port 0 are dedicated for the external capacitors’ connections. The capacitor Cmod assigned to pin 5
of port 0 is connected to the internal left analog bus. The capacitor Cmod assigned to pin7 of port 0
is connected to the internal right analog bus. You can also use a potentiometer in parallel to Cmod,
but this is optional. If the potentiometer RV2 is needed for the left channel, put shunts on J6. If the
potentiometer RV3 is needed for the right channel, put shunts on J7. By default, resistors of R55 and
R56 are not populated.
Figure 3-2. Schematics
32.768 kHz External Crystal Oscillator
The CY8C28XXX has multiple clock sources. These include the phase locked loop (PLL), internal
main oscillator (IMO), internal low speed oscillator (ILO), and 32.768 kHz external crystal oscillator
(ECO) for precision, programmable clocking. The clocks, together with programmable clock dividers
(as a System Resource), provide the flexibility to integrate almost any timing requirement into the
PSoC device.
Vad
desired voltage is acquired.
j
min
=
CY3280-28XXX Universal CapSense® Controller Development Kit Guide, Spec. # 001-57457 Rev. **
1.216
×
⎛
⎝
1
+
------------------------------------------------- -
R23
+
R57 RV1
R58
||
max
⎞
⎠
=
1.216
×
⎛
⎝
1
+
-----------------------------------------
1.5k
+
3.9k
5.1k 10k
||
⎞
⎠
=
2.19V
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