MCB1114 Keil, MCB1114 Datasheet - Page 28
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MCB1114
Manufacturer Part Number
MCB1114
Description
BOARD EVALUATION FOR NXP LPC1114
Manufacturer
Keil
Datasheet
1.MCB1114.pdf
(53 pages)
Specifications of MCB1114
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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NXP Semiconductors
LPC1111_12_13_14_0
Objective data sheet
7.16.7 Memory mapping control
7.17 Emulation and debugging
The Cortex-M0 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the NVIC.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M0 address
space. The vector table must be located on a 128 word (512 byte) boundary.
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four
breakpoints and two watchpoints is supported.
Rev. 00.11 — 13 November 2009
LPC1111/12/13/14
© NXP B.V. 2009. All rights reserved.
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