LMC660CM National Semiconductor, LMC660CM Datasheet - Page 8

• Manufacturer Part Number: LMC660CM
• Description: OP AMP, QUAD CMOS, SMD, SOIC14, 660
• Manufacturer: National Semiconductor

Specifications of LMC660CM

• Op Amp Type: Low Input Bias
• No. Of Amplifiers: 4
• Bandwidth: 0.5MHz
• Slew Rate: 1.1V/µs
• Supply Voltage Range: 4.75V To 15.5V
• Amplifier Case Style: SOIC
• No. Of Pins: 14
• Operating Temperature: RoHS Compliant

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Application Hints
CAPACITIVE LOAD TOLERANCE
Like many other op amps, the LMC660 may oscillate when
its applied load appears capacitive. The threshold of oscilla-
tion varies both with load and circuit gain. The configuration
most sensitive to oscillation is a unity-gain follower. See
Typical Performance Characteristics.
The load capacitance interacts with the op amp’s output
resistance to create an additional pole. If this pole frequency
is sufficiently low, it will degrade the op amp’s phase margin
so that the amplifier is no longer stable at low gains. As
shown in Figure 3, the addition of a small resistor (50Ω to
100Ω) in series with the op amp’s output, and a capacitor (5
pF to 10 pF) from inverting input to output pins, returns the
phase margin to a safe value without interfering with lower-
frequency circuit operation. Thus larger values of capaci-
tance can be tolerated without oscillation. Note that in all
cases, the output will ring heavily when the load capacitance
is near the threshold for oscillation.
Capacitive load driving capability is enhanced by using a pull
up resistor to V
conducting 500 µA or more will significantly improve capaci-
tive load responses. The value of the pull up resistor must be
determined based on the current sinking capability of the
amplifier with respect to the desired output swing. Open loop
gain of the amplifier can also be affected by the pull up
resistor (see Electrical Characteristics).
PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the LMC662, typically less
than 0.04 pA, it is essential to have an excellent layout.
Fortunately, the techniques for obtaining low leakages are
FIGURE 3. Rx, Cx Improve Capacitive Load Tolerance
FIGURE 4. Compensating for Large Capacitive Loads
+
with a Pull Up Resistor
(Figure 4). Typically a pull up resistor
(Continued)
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quite simple. First, the user must not ignore the surface
leakage of the PC board, even though it may sometimes
appear acceptably low, because under conditions of high
humidity or dust or contamination, the surface leakage will
be appreciable.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC660’s inputs and the
terminals of capacitors, diodes, conductors, resistors, relay
terminals, etc. connected to the op-amp’s inputs. See Figure
5. To have a significant effect, guard rings should be placed
on both the top and bottom of the PC board. This PC foil
must then be connected to a voltage which is at the same
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 10
mally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of an input. This
would cause a 100 times degradation from the LMC660’s
actual performance. However, if a guard ring is held within
5 mV of the inputs, then even a resistance of 10
cause only 0.05 pA of leakage current, or perhaps a minor
(2:1) degradation of the amplifier’s performance. See Figure
6a, Figure 6b, Figure 6c for typical connections of guard
rings for standard op-amp configurations. If both inputs are
active and at high impedance, the guard can be tied to
ground and still provide some protection; see Figures 6, 6d.
FIGURE 5. Example, using the LMC660,
of Guard Ring in P.C. Board Layout
12
Ω, which is nor-
11
Ω would
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