DP83848VYB National Semiconductor, DP83848VYB Datasheet
DP83848VYB
Specifications of DP83848VYB
Available stocks
Related parts for DP83848VYB
DP83848VYB Summary of contents
Page 1
... The DP83848VYB was designed to meet the challenge of these new applications with an extended temperature perfor- mance that goes beyond the typical Industrial temperature range. The DP83848VYB is a highly reliable, feature rich, ro- bust device which meets IEEE 802.3u standards over an EXTENDED temperature range of -40°C to 105°C. This de- ...
Page 2
Block Diagram www.national.com 2 30011701 ...
Page 3
General Description .............................................................................................................................. 1 Applications ......................................................................................................................................... 1 Features .............................................................................................................................................. 1 System Diagram ................................................................................................................................... 1 Block Diagram ...................................................................................................................................... 2 Pin Layout ........................................................................................................................................... 6 1.0 Pin Descriptions .............................................................................................................................. 7 1.1 SERIAL MANAGEMENT INTERFACE ............................................................................................. 7 1.2 MAC DATA INTERFACE ................................................................................................................ 7 1.3 ...
Page 4
Link Integrity Monitor .......................................................................................... 25 4.2.11 Bad SSD Detection ............................................................................................................... 25 4.3 10BASE-T TRANSCEIVER MODULE ............................................................................................ 25 4.3.1 Operational Modes .................................................................................................................. 25 4.3.2 Smart Squelch ........................................................................................................................ 26 4.3.3 Collision Detection and SQE .................................................................................................... 26 4.3.4 Carrier Sense ......................................................................................................................... ...
Page 5
Mb/s Serial Mode Transmit Timing ...................................................................................... 64 8.2.14 10 Mb/s Serial Mode Receive Timing ...................................................................................... 64 8.2.15 10BASE-T Transmit Timing (Start of Packet) ............................................................................ 65 8.2.16 10BASE-T Transmit Timing (End of Packet) ............................................................................. 65 8.2.17 10BASE-T Receive Timing ...
Page 6
Pin Layout www.national.com Top View NS Package Number VXH48A 6 30011755 ...
Page 7
... TXD_3 RX_CLK O 38 RX_DV All DP83848VYB signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of the I/O cells for each pin. Type: I Type: O Type: I/O Type OD Type: PD,PU Internal Pulldown/Pullup Type: S MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/ output serial interface which may be asynchronous to transmit and receive clocks ...
Page 8
... Mb/s SNI mode. CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83848VYB and must be connected MHz 0.005% (±50 ppm) clock source. The DP83848VYB supports either an external crystal resonator connected across pins X1 and X2 external CMOS-level oscillator source connected to pin X1 only. ...
Page 9
... This pin has a weak internal pullup. Pin # 29 RESET: Active Low input that initializes or re-initializes the DP83848VYB. Asserting this pin low for at least 1 µs will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each bit in the Register Block section ...
Page 10
... AN0 and AN1 pins. AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83848VYB according to the following table. The value on these pins is set by connecting the input pins to GND ( should NEVER be connected directly to GND or V The value set at this input is latched into the DP83848VYB at Hardware-Reset. ...
Page 11
Signal Name Type LED_CFG (CRS MDIX_EN (RX_ER 1.8 10 Mb/s AND 100 Mb/s PMD INTERFACE Signal Name Type Pin # TD-, TD+ I/O RD-, RD+ I/O 1.9 SPECIAL CONNECTIONS Signal Name Type Pin # ...
Page 12
PACKAGE PIN ASSIGNMENTS VBH48A Pin # Pin Name 1 TX_CLK 2 TX_EN 3 TXD_0 4 TXD_1 5 TXD_2 6 TXD_3/SNI_MODE 7 PWR_DOWN/INT 8 TCK 9 TDO 10 TMS 11 TRST# 12 TDI ...
Page 13
... Auto-Negotiation abil- ity, and Extended Register Capability. These bits are perma- nently set to indicate the full functionality of the DP83848VYB (only the 100BASE-T4 bit is not set since the DP83848VYB does not support that function). The BMSR also provides status on: • ...
Page 14
... PHYAD3 46 PHYAD4 The DP83848VYB can be set to respond to any of 32 possible PHY addresses via strap pins. The information is latched into the PHYCR register (address 19h, bits [4:0]) at device power- up and hardware reset. The PHY Address pins are shared with the RXD and COL pins. Each DP83848VYB or port shar- ing an MDIO bus in a system must have a unique physical address ...
Page 15
... LED INTERFACE The DP83848VYB supports three configurable Light Emitting Diode (LED) pins. The device supports three LED configura- tions: Link, Speed, Activity and Collision. Function are multi- LED_CFG[1] LED_CFG[0] (bit 5) Mode (bit 6) or (pin 40) 1 don't care The LED_LINK pin in Mode 1 indicates the link status of the port ...
Page 16
... Mb/s per port when operating in either 100BASE-TX or 100BASE-FX. Because the CSMA/CD protocol does not ap- ply to full-duplex operation, the DP83848VYB disables its own internal collision sensing and reporting functions and modifies the behavior of Carrier Sense (CRS) such that it indicates only receive activity ...
Page 17
... Collisions are reported by the COL signal on the MII. If the DP83848VYB is transmitting in 10 Mb/s mode when a collision is detected, the collision is not reported until seven bits have been received while in the collision state. This pre- vents a collision being reported incorrectly due to noise on the network ...
Page 18
... MDIO signal during the first bit of Turnaround. The addressed DP83848VYB drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 3 shows the timing relationship between MDC and the MDIO ...
Page 19
... MDIO in conjunction with a continuous MDC, or the management access made to determine whether Preamble Suppression is supported. While the DP83848VYB requires an initial preamble se- quence of 32 bits for management initialization, it does not require a full 32-bit sequence between each subsequent transaction. A minimum of one idle bit between management transactions is required as specified in the IEEE 802 ...
Page 20
... The bypass option for the functional blocks within the 100BASE-TX transmitter provides flexibility for applications where data conversion is not always required. The DP83848VYB implements the 100BASE-TX transmit state machine diagram as specified in the IEEE 802.3u Standard, Clause 24. FIGURE 5. 100BASE-TX Transmit Block Diagram ...
Page 21
... LFSR is X-ORd with the serial NRZ data from the code-group encoder. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at certain frequencies by as much as 20 dB. The DP83848VYB uses the PHY_ID (pins PHYAD [4:1]) to set a unique seed value. 21 0000 ...
Page 22
... AC coupling magnetics to ensure TP-PMD Standard compliant transition times (3 ns < Tr < 5 ns). The 100BASE-TX transmit TP-PMD function within the DP83848VYB is capable of sourcing only MLT-3 encoded data. Binary output from the PMD Output Pair is not possible in 100 Mb/s mode. 4.2 100BASE-TX RECEIVER ...
Page 23
... The DP83848VYB utilizes an extremely robust equalization scheme referred as ‘Digital Adaptive Equalization.’ The Digital Equalizer removes ISI (inter symbol interference) from the receive data stream by continuously adapting to pro- vide a filter with the inverse frequency response of the chan- nel ...
Page 24
... FIGURE 7. EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 Meters of CAT 5 Cable 4.2.2.2 Base Line Wander Compensation The DP83848VYB is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW) compensation. The BLW compensation block can successfully recover the TP- PMD defined “killer” pattern. ...
Page 25
... In Half Duplex mode the DP83848VYB functions as a stan- dard IEEE 802.3 10BASE-T transceiver supporting the CS- MA/CD protocol. Full Duplex Mode In Full Duplex mode the DP83848VYB is capable of simulta- neously transmitting and receiving without asserting the col- lision signal. The DP83848VYB's 10 Mb/s ENDEC is designed to encode and decode simultaneously. ...
Page 26
... Jabber Function The jabber function monitors the DP83848VYB's output and disables the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if the transmitter is active for approximately 85 ms ...
Page 27
... Transmit and Receive Filtering External 10BASE-T filters are not required when using the DP83848VYB, as the required signal conditioning is integrat- ed into the device. Only isolation transformers and impedance matching resis- tors are required for the 10BASE-T transmit and receive interface ...
Page 28
... ESD events. See section 8.0 AC and DC Specifications for ESD rating. 5.3 CLOCK IN (X1) REQUIREMENTS The DP83848VYB supports an external CMOS level oscilla- tor source or a crystal resonator device. Oscillator If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating ...
Page 29
... Frequency Stability Load Capacitance 25 5.4 POWER FEEDBACK CIRCUIT To ensure correct operation for the DP83848VYB, parallel caps with values of 10 µF and 0.1 µF should be placed close to pin 23 (PFBOUT) of the device. Pin 18(PFBIN1), pin 37 (PFBIN2), pin 23 (PFBIN3) and pin 54 (PFBIN4) must be connected to pin 31 (PFBOUT), each pin requires a small capacitor (.1 µ ...
Page 30
... PWRDOWN_INT pin will deassert. 5.6 ENERGY DETECT MODE When Energy Detect is enabled and there is no activity on the cable, the DP83848VYB will remain in a low power mode while monitoring the transmission line. Activity on the line will cause the DP83848VYB to go through a normal power up sequence ...
Page 31
FIGURE 13. Top View, Thermal Vias for GNDPAD, Pin 49 31 30011714 www.national.com ...
Page 32
... Reset Operation The DP83848VYB includes an internal power-on reset (POR) function and does not need to be explicitly reset for normal operation after power up. If required during normal operation, the device can be reset by a hardware or software reset. 6.1 HARDWARE RESET A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 µ ...
Page 33
Register Block Offset Access Hex Decimal 00h 0 RW 01h 1 RO 02h 2 RO 03h 3 RO 04h 4 RW 05h 5 RW 05h 5 RW 06h 6 RW 07h 7 RW 08h-Fh 8-15 10h 16 RO 11h ...
Page 34
www.national.com 34 ...
Page 35
35 www.national.com ...
Page 36
REGISTER DEFINITION In the register definitions under the ‘Default’ heading, the following definitions hold true: — Read Write access — Register sets on event occurrence and Self-Clears when event ends — RW/SC = ReadW rite ...
Page 37
Basic Mode Control Register (BMCR) TABLE 12. Basic Mode Control Register (BMCR), address 0x00h Bit Bit Name Default 15 RESET 0, RW/SC 14 LOOPBACK SPEED SELECTION Strap AUTO-NEGOTIATION Strap, RW ENABLE 11 POWER DOWN ...
Page 38
Bit Bit Name Default 7 COLLISION TEST 6:0 RESERVED 7.1.2 Basic Mode Status Register (BMSR) TABLE 13. Basic Mode Status Register (BMSR), address 0x01h Bit Bit Name Default 15 100BASE-T4 0, RO/P 14 100BASE-TX 1, RO/P FULL DUPLEX 13 100BASE-TX ...
Page 39
... The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848VYB. The Identifier consists of a con- catenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management ...
Page 40
Bit Bit Name 10 PAUSE TX_FD 10_FD 5 10 4:0 SELECTOR <00001>, RW 7.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the Link Partner as received ...
Page 41
Bit Bit Name Default 10 PAUSE TX_FD 10_FD 4:0 SELECTOR <0 0000>, RO 7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) ...
Page 42
Auto-Negotiate Expansion Register (ANER) This register contains additional Local Device and Link Partner status information. TABLE 19. Auto-Negotiate Expansion Register (ANER), address 0x06h Bit Bit Name 15:5 RESERVED 4 PDF 3 LP_NP_ABLE 2 NP_ABLE 1 PAGE_RX 0, RO/COR 0 ...
Page 43
EXTENDED REGISTERS 7.2.1 PHY Status Register (PHYSTS) This register provides a single location within the register set for quick access to commonly accessed information. TABLE 21. PHY Status Register (PHYSTS), address 10h Bit Bit Name 15 RESERVED 14 MDIX ...
Page 44
Bit Bit Name 5 JABBER DETECT 4 AUTO-NEG COMPLETE 3 LOOPBACK STATUS 2 DUPLEX STATUS 1 SPEED STATUS 0 LINK STATUS www.national.com Default 0, RO Jabber Detect: This bit only has meaning in 10 Mb/s mode. This bit is a ...
Page 45
MII Interrupt Control Register (MICR) This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Energy Detect State Change, Link State Change, Speed Status Change, Duplex Status Change, Auto-Negotiation Complete or any of the ...
Page 46
MII Interrupt Status and Misc. Control Register (MISR) This register contains event status and enables for the interrupt function event has occurred since the last read of this register, the corresponding status bit will be set. If ...
Page 47
False Carrier Sense Counter Register (FCSCR) This counter provides information required to implement the “False Carriers” attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification. TABLE 24. False Carrier Sense Counter Register (FCSCR), ...
Page 48
Mb/s PCS Configuration and Status Register (PCSR) This register contains control and status information for the 100BASE Physical Coding Sublayer. TABLE 26. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16h Bit Bit Name Default 15:13 RESERVED ...
Page 49
... MHz RMII clock and the recovered data. The following values indicate the tolerance in bits for a single packet. The minimum setting allows for standard Ethernet frame sizes at +/-50ppm accuracy for both RMII and Receive clocks. For greater frequency tolerance the packet lengths may be scaled (i ...
Page 50
Bit Bit Name Default 13 PAUSE_RX 12 PAUSE_TX 11 BIST_FE 0, RW/SC 10 PSR_15 9 BIST_STATUS 0, LL/RO 8 BIST_START 7 BP_STRETCH www.national.com 0, RO Pause Receive Negotiated: Indicates that pause receive should be enabled in the MAC. Based on ...
Page 51
Bit Bit Name Default 6 LED_CNFG[ LED_CNFG[0] Strap, RW 4:0 PHYADDR[4:0] Strap, RW 7.2.10 10 Base-T Status/Control Register (10BTSCR) This register is used for control and status for 10BASE-T device operation. TABLE 30. 10Base-T Status/Control Register (10BTSCR), ...
Page 52
Bit Bit Name 4 POLARITY 3 RESERVED 2 RESERVED 1 HEARTBEAT_DIS 0 JABBER_DIS www.national.com Default RO/LH 10Mb Polarity Status: This bit is a duplication of bit 12 in the PHYSTS register. Both bits will be cleared upon a read of ...
Page 53
CD Test and BIST Extensions Register (CDCTRL1) This register controls test modes for the 10BASE-T Common Driver. In addition it contains extended control and status for the packet BIST function. TABLE 31. CD Test and BIST Extensions Register (CDCTRL1), ...
Page 54
Bit Bit Name 12 ED_MAN 11 ED_BURST_DIS 10 ED_PWR_STATE 9 ED_ERR_MET 8 ED_DATA_MET 7:4 ED_ERR_COUNT 3:0 ED_DATA_COUNT www.national.com Default 0, RW/SC Energy Detect Manual Power Up/Down: Begin power up/down sequence when this bit is asserted. When set, the Energy Detect ...
Page 55
... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Storage Temperature (T ) STG Max. Die Temperature 8.0 AC and DC Specifications Note: All parameters are guaranteed by test, statistical analysis or design. ...
Page 56
Pin Symbol Parameter Types I Supply 10BASE-T dd10 (Full Duplex) I Supply Power Down Mode dd Note 1: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply ...
Page 57
AC SPECIFICATIONS 8.2.1 Power Up Timing Parameter Description T2.1.1 Post Power Up Stabilization time prior to MDC preamble for register accesses T2.1.2 Hardware Configuration Latch-in Time from power up T2.1.3 Hardware Configuration pins transition to output drivers Note: In ...
Page 58
Reset Timing Parameter Description T2.2.1 Post RESET Stabilization time prior to MDC preamble for register accesses T2.2.2 Hardware Configuration Latch-in Time from the Deassertion of RESET (either soft or hard) T2.2.3 Hardware Configuration pins transition to output drivers T2.2.4 ...
Page 59
MII Serial Management Timing Parameter Description T2.3.1 MDC to MDIO (Output) Delay Time T2.3.2 MDIO (Input) to MDC Setup Time T2.3.3 MDIO (Input) to MDC Hold Time T2.3.4 MDC Frequency 8.2.4 100 Mb/s MII Transmit Timing Parameter Description T2.4.1 ...
Page 60
Mb/s MII Receive Timing Parameter Description T2.5.1 RX_CLK High/Low Time T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. ...
Page 61
Transmit Packet Deassertion Timing Parameter Description T2.7.1 TX_CLK to PMD Output Pair Deassertion 100BASE-TX and 100BASE-FX modes Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN ...
Page 62
Receive Packet Latency Timing Parameter Description T2.9.1 Carrier Sense ON Delay T2.9.2 Receive Data Latency Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion ...
Page 63
Mb/s MII Transmit Timing Parameter Description T2.11.1 TX_CLK High/Low Time T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK fall T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rise Note: An attached Mac should drive the transmit signals using the positive ...
Page 64
Mb/s Serial Mode Transmit Timing Parameter Description T2.13.1 TX_CLK High Time T2.13.2 TX_CLK Low Time T2.13.3 TXD_0, TX_EN Data Setup to TX_CLK rise T2.13.4 TXD_0, TX_EN Data Hold from TX_CLK rise 8.2.14 10 Mb/s Serial Mode Receive Timing ...
Page 65
Transmit Timing (Start of Packet) Parameter Description T2.15.1 Transmit Output Delay from the Falling Edge of TX_CLK T2.15.2 Transmit Output Delay from the Rising Edge of TX_CLK Note: 1 bit time = 100 Mb/s. 8.2.16 ...
Page 66
Receive Timing (Start of Packet) Parameter Description T2.17.1 Carrier Sense Turn On Delay (PMD Input Pair to CRS) T2.17.2 RX_DV Latency T2.17.3 Receive Data Latency Note: 10BASE-T RX_DV Latency is measured from first bit of preamble on the ...
Page 67
Mb/s Heartbeat Timing Parameter Description T2.19.1 CD Heartbeat Delay T2.19.2 CD Heartbeat Duration 8.2.20 10 Mb/s Jabber Timing Parameter Description T2.20.1 Jabber Activation Time T2.20.2 Jabber Deactivation Time Notes Min 10 Mb/s half-duplex mode 10 Mb/s half-duplex mode ...
Page 68
Normal Link Pulse Timing Parameter Description T2.21.1 Pulse Width T2.21.2 Pulse Period Note: These specifications represent transmit timings. 8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameter Description T2.22.1 Clock, Data Pulse Width T2.22.2 Clock Pulse to Clock Pulse ...
Page 69
Signal Detect Timing Parameter Description T2.23.1 SD Internal Turn-on Time T2.23.2 SD Internal Turn-off Time Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant. 8.2.24 100 Mb/s Internal Loopback Timing Parameter Description T2.24.1 TX_EN to ...
Page 70
Mb/s Internal Loopback Timing Parameter Description T2.25.1 TX_EN to RX_DV Loopback Note: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. www.national.com Notes 10 Mb/s internal loopback mode 70 30011744 Min Typ Max ...
Page 71
RMII Transmit Timing Parameter Description T2.26.1 X1 Clock Period T2.26.2 TXD[1:0], TX_EN, Data Setup to X1 rising T2.26.3 TXD[1:0], TX_EN, Data Hold from X1 rising T2.26.4 X1 Clock to PMD Output Pair Latency Notes Min 50 MHz Reference Clock ...
Page 72
RMII Receive Timing Parameter Description T2.27.1 X1 Clock Period T2.27.2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising T2.27.3 CRS ON delay (100Mb) T2.27.4 CRS OFF delay (100Mb) T2.27.5 RXD[1:0] and RX_ER latency (100Mb) Note: Per the ...
Page 73
Isolation Timing Parameter Description T2.28.1 From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal mode T2.28.2 From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode 8.2.29 ...
Page 74
Mb TX_CLK Timing Parameter Description T2.30 TX_CLK delay Note TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data. www.national.com Notes Min ...
Page 75
Physical Dimensions inches (millimeters) unless otherwise noted Lead Quad Frame Package (LQFP) NS Package Number VXH48A 75 www.national.com ...
Page 76
... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock Conditioners www.national.com/timing Data Converters www.national.com/adc Displays www.national.com/displays Ethernet www.national.com/ethernet Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www ...