LM5101CMA National Semiconductor, LM5101CMA Datasheet
LM5101CMA
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LM5101CMA Summary of contents
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... Features ■ Drives both a high-side and low-side N-Channel MOSFETs ■ Independent high and low driver logic inputs Simplified Block Diagram © 2010 National Semiconductor Corporation LM5100A/B/C LM5101A/B/C ■ Bootstrap supply voltage up to 118V DC ■ Fast propagation times (25 ns typical) ■ ...
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Input/Output Options Part Number LM5100A LM5101A LM5100B LM5101B LM5100C LM5101C Connection Diagrams www.national.com Input Thresholds CMOS TTL CMOS TTL CMOS TTL 20203101 20203135 20203136 2 Peak Output Current 20203137 20203102 ...
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... LM5100A/LM5101AMR PSOP 8 LM5100A/LM5101AMRX PSOP 8 LM5100A /LM5101ASD LLP 10 LM5100A/LM5101ASDX LLP 10 LM5100B/LM5101BMA SOIC 8 LM5100B/LM5101BMAX SOIC 8 LM5100B/LM5101BSD LLP 10 LM5100B/LM5101BSDX LLP 10 LM5100C/LM5101CMA SOIC 8 LM5100C/LM5101CMAX SOIC 8 LM5100C /LM5101CSD LLP 10 LM5100C/LM5101CSDX LLP 10 LM5100C/LM5101CMYE eMSOP-8 LM5100C/LM5101CMY eMSOP-8 LM5100C/LM5101CMYX eMSOP-8 LM5101ASD-1 LLP 8 LM5101ASDX-1 LLP 8 NSC Package Drawing M08A 95 units shipped in anti static rails M08A 2500 shipped in Tape & ...
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Pin Descriptions Pin # SOIC-8 PSOP-8 LLP-8 LLP- ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDD to VSS Input LO Output HO Output VSS (Note VSS Electrical Characteristics Limits in standard type are for T = 25°C only; limits in boldface type apply over the junction temperature (T J +125° ...
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Symbol Parameter I Peak Pulldown Current LM5100A/LM5101A OLL Peak Pulldown Current LM5100B/LM5101B Peak Pulldown Current LM5100C/LM5101C THERMAL RESISTANCE θ Junction to Ambient JA Switching Characteristics Limits in standard type are for T = 25°C only; limits in boldface type apply ...
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Symbol Parameter t Minimum Input Pulse Width that Changes PW the Output t Bootstrap Diode Reverse Recovery Time I BS Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under ...
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LM5100A/B Frequency DD Operating Current vs Temperature Quiescent Current vs Supply Voltage www.national.com LM5101A/B/C I 20203109 I HB 20203111 Quiescent Current vs Temperature 20203118 8 vs Frequency DD 20203110 vs Frequency 20203114 20203119 ...
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Undervoltage Rising Thresholds vs Temperature Bootstrap Diode Forward Voltage LM5101A/B/C Input Threshold vs Temperature Undervoltage Threshold Hysteresis vs Temperature 20203122 LM5100A/B/C Input Threshold vs Temperature 20203115 LM5100A/B/C Input Threshold vs VDD 20203124 9 20203117 20203123 20203125 www.national.com ...
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LM5101A/B/C Input Threshold vs VDD LM5101A/B/C Propagation Delay vs Temperature LO & HO Gate Drive - Low Level Output Voltage vs Temperature www.national.com LM5100A/B/C Propagation Delay vs Temperature 20203126 LO & HO Gate Drive - High Level Output Voltage vs ...
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LO & HO Gate Drive - Output Low Voltage vs VDD Timing Diagram 20203132 FIGURE 2. 11 20203104 www.national.com ...
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Layout Considerations The optimum performance of high and low-side gate drivers cannot be achieved without taking due considerations during circuit board layout. Following points are emphasized. 1. Low ESR / ESL capacitors must be connected close to the IC, between ...
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Power Dissipation Considerations The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are related to the switching frequency (f), output load capac- itance on LO and HO ...
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Physical Dimensions Controlling dimension is inch. Values are millimeters. Notes: Unless otherwise specified. 1. Standard lead finish to be 200 microinches/5.08 micrometers minimum lead/tin (solder) on copper. 2. Dimension does not include mold flash. Reference JEDEC ...
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... Notes: Unless otherwise specified. 1. For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor web page (www.national.com). 2. Maximum allowable metal burr on lead tips at the package edges is 76 microns JEDEC registration as of May 2003. LLP-8 Outline Drawing ...
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Outline Drawing NS Package Number MUY08A 16 ...
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Notes 17 www.national.com ...
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