DSPIC30F4011-20E/P Microchip Technology, DSPIC30F4011-20E/P Datasheet - Page 16
![IC, DSC, 16BIT, 48KB, 40MHZ, 5.5V, DIP40](/photos/6/61/66192/150-40-dip_sml.jpg)
DSPIC30F4011-20E/P
Manufacturer Part Number
DSPIC30F4011-20E/P
Description
IC, DSC, 16BIT, 48KB, 40MHZ, 5.5V, DIP40
Manufacturer
Microchip Technology
Series
DsPIC30Fr
Datasheets
1.DSPIC30F2011-20IP.pdf
(26 pages)
2.DSPIC30F4012-30ISO.pdf
(238 pages)
3.DSPIC30F4012-30ISO.pdf
(18 pages)
4.DSPIC30F4012-30ISO.pdf
(6 pages)
5.DSPIC30F4012-30ISO.pdf
(16 pages)
6.DSPIC30F4012-30ISO.pdf
(22 pages)
Specifications of DSPIC30F4011-20E/P
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
48KB
Supply Voltage Range
2.5V To 5.5V
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F003 - MODULE SOCKET DSPIC30F 40DIPACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
DSPIC30F4011-20EP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F4011-20E/P
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
DSPIC30F4011-20E/PT
Manufacturer:
Microchip Technology
Quantity:
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Part Number:
DSPIC30F4011-20E/PT
Manufacturer:
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Quantity:
20 000
dsPIC30F Family Reference Manual
35.3.3.1
DS70272B-page 35-16
Frame Master and Frame Slave Modes
The SPI1 module supports two framed modes of operation. In Framed Master mode, the SPI1
module generates the frame synchronization pulse and provides this pulse to other devices at
the SS1 pin. In Framed Slave mode, the SPI1 module uses a frame synchronization pulse
received at the SS1 pin.
The following four Framed SPI modes are supported in conjunction with the unframed Master
and Slave modes:
• SPI Master, Frame Master
• SPI Master, Frame Slave
• SPI Slave, Frame Master
• SPI Slave, Frame Slave
These modes determine whether or not the SPI1 module generates the serial clock and the
frame synchronization pulse.
When FRMEN (SPI1CON2<15>) = 1 and MSTEN (SPI1CON1<5>) = 1, the SCK1 pin becomes
an output and the SPI clock at SCK1 becomes a free running clock.
When FRMEN = 1 and MSTEN = 0, the SCK1 pin becomes an input. The source clock provided
to the SCK1 pin is assumed to be a free running clock.
The polarity of the clock is selected by the CKP (SPI1CON1<6>) bit. The CKE (SPI1CON1<8>)
bit is not used for the Framed SPI modes and should be programmed to ‘0’ by the user
application.
When CKP = 0, the frame synchronization pulse output and the SDO1 data output change on
the rising edge of the clock pulses at the SCK1 pin. Input data is sampled at the SDI1 input pin
on the falling edge of the serial clock.
When CKP = 1, the frame synchronization pulse output and the SDO1 data output change on
the falling edge of the clock pulses at the SCK1 pin. Input data is sampled at the SDI1 input pin
on the rising edge of the serial clock.
When SPIFSD (SPI1CON2<14>) = 0, the SPI1 module is in the Frame Master mode of
operation. In this mode, the frame sync pulse is initiated by the module when the user application
writes the transmit data to the SPI1BUF location (thus writing the SPI1TXB register with transmit
data). At the end of the frame synchronization pulse, the SPI1TXB is transferred to the SPI1SR
and data transmission or reception begins.
When SPIFSD = 1, the module is in Framed Slave mode. In this mode, the frame synchronization
pulse is generated by an external source. When the module samples the frame synchronization
pulse, it will transfer the contents of the SPI1TXB register to the SPI1SR and data transmission
or reception begins. The user application must make sure that the correct transmission data is
loaded into the SPI1BUF before the frame synchronization pulse is received.
Note:
Note:
The use of the SS1 and SCK1 pins is mandatory in all Framed SPI modes.
Receiving a frame synchronization pulse will start a transmission regardless of
whether data was written to SPI1BUF. If no write was performed, the old contents of
the SPI1TXB will be transmitted.
© 2008 Microchip Technology Inc.