DSPIC33FJ128GP802-E/MM Microchip Technology, DSPIC33FJ128GP802-E/MM Datasheet - Page 73

• Manufacturer Part Number: DSPIC33FJ128GP802-E/MM
• Description: IC, DSC, 16BIT, 128KB 40MHZ, 3.6V, QFN28
• Manufacturer: Microchip Technology
• Series: DsPIC33Fr

Specifications of DSPIC33FJ128GP802-E/MM

• Core Frequency: 40MHz
• Core Supply Voltage: 3.6V
• No. Of I/o's: 21
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +125°C
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b, D/A 4x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Rohs Compliant: Yes
• Package: 28QFN-S EP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 10-chx10-bit|10-chx12-bit
• On-chip Dac: 2-chx16-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5.0
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 devices contain
internal Flash program memory for storing and
executing application code. The memory is readable,
writable and erasable during normal operation over the
entire V
Flash memory can be programmed in two ways:
• In-Circuit Serial Programming™ (ICSP™)
• Run-Time Self-Programming (RTSP)
ICSP
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04, to be serially pro-
grammed while in the end application circuit. This is
done with two lines for programming clock and
FIGURE 5-1:
 2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
programming capability
Note 1: This data sheet summarizes the features
DD
allows
2: Some registers and associated bits
FLASH PROGRAM MEMORY
range.
of
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 5. Flash Program-
ming” (DS70191) of the “dsPIC33F/
PIC24H
which is available from the Microchip
website (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
any
Using
Program Counter
Using
Table Instruction
User/Configuration
Space Select
the
ADDRESSING FOR TABLE REGISTERS
Family
of
dsPIC33FJ32GP302/304,
the
Reference
following
1/0
0
TBLPAG Reg
Manual”,
8 bits
devices,
and
Preliminary
Program Counter
24-bit EA
24 bits
programming data (one of the alternate programming
pin pairs: PGECx/PGEDx), and three other lines for
power (V
This allows customers to manufacture boards with
unprogrammed devices and then program the digital
signal controller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
application can write program memory data either in
blocks or ‘rows’ of 64 instructions (192 bytes) at a time
or a single program memory word, and erase program
memory in blocks or ‘pages’ of 512 instructions (1536
bytes) at a time.
5.1
Regardless of the method used, all programming of
Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits <7:0> of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to bits <15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits <23:16> of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
Working Reg EA
16 bits
Table Instructions and Flash
Programming
DD
), ground (V
0
SS
) and Master Clear (MCLR).
Byte
Select
DS70292D-page 73