LMF100CIWM National Semiconductor, LMF100CIWM Datasheet - Page 23

• Manufacturer Part Number: LMF100CIWM
• Description: IC, SW CAP FILTER, 100KHZ, SOIC-20
• Manufacturer: National Semiconductor

Specifications of LMF100CIWM

• Ic Filter Type: Switched Capacitor
• Filter Order: 4th
• No. Of Filters: 2
• Cutoff Frequency: 40kHz
• Program Clock Frequency Typ: 3.5MHz
• Supply Voltage Range: 4V To 15V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.0 Applications Information
3.2 SINGLE SUPPLY OPERATION
The LMF100 can also operate with a single-ended power
supply. Figure 20 shows the example filter with a
single-ended power supply. V
nected to the positive power supply (4 to 15 volts), and V
and V
tied to V
should be very “clean”, as any noise appearing on it will be
treated as an input to the filter. It can be derived from the
supply voltage with a pair of resistors and a bypass capacitor
( Figure 21a ), or a low-impedance half-supply voltage can be
made using a three-terminal voltage regulator or an opera-
tional amplifier ( Figure 21b and Figure 21c ). The passive re-
sistor divider with a bypass capacitor is sufficient for many
applications, provided that the time constant is long enough
to reject any power supply noise. It is also important that the
half-supply reference present a low impedance to the clock
frequency, so at very low clock frequencies the regulator or
op-amp approaches may be preferable because they will re-
quire smaller capacitors to filter the clock frequency. The
main power supply voltage should be clean (preferably regu-
lated) and bypassed with 0.1 µF.
3.3 DYNAMIC CONSIDERATIONS
The maximum signal handling capability of the LMF100, like
that of any active filter, is limited by the power supply volt-
ages used. The amplifiers in the LMF100 are able to swing to
within about 1 volt of the supplies, so the input signals must
be kept small enough that none of the outputs will exceed
these limits. If the LMF100 is operating on
ample, the outputs will clip at about 8V
put voltage multiplied by the filter gain should therefore be
less than 8V
Note that if the filter Q is high, the gain at the lowpass or
highpass outputs will be much greater than the nominal filter
gain ( Figure 6 ). As an example, a lowpass filter with a Q of
10 will have a 20 dB peak in its amplitude response at f
the nominal gain of the filter (H
f
be less than 800 mV
volt supplies.
Also note that one output can have a reasonable small volt-
age on it while another is saturated. This is most likely for a
circuit such as the notch in Mode 1 ( Figure 7 ). The notch out-
put will be very small at f
large signal to the input. However, the bandpass will have its
maximum gain at f
clips, the performance at the other outputs will be degraded,
so avoid overdriving any filter section, even ones whose out-
0
will be 10. The maximum input signal at f
(a) Resistive Divider with
D
− are connected to ground. The A
Decoupling Capacitor
+
/2 for single supply operation. This half-supply point
p-p
.
0
and can clip if overdriven. If one output
p-p
0
when the circuit is operated on
FIGURE 21. Three Ways of Generating V
, so it might appear safe to apply a
DS005645-32
A
OLP
+ and V
) is equal to 1, the gain at
p-p
D
. The maximum in-
+ are again con-
GND
0
±
5 volts, for ex-
must therefore
pin must be
(Continued)
(b) Voltage Regulator
0
±
A
. If
−
5
23
puts are not being directly used. Accompanying Figures 7, 8,
9, 10, 11, 12, 13, 14, 15, 16 and Figure 17 are equations la-
beled “circuit dynamics”, which relate the Q and the gains at
the various outputs. These should be consulted to determine
peak circuit gains and maximum allowable signals for a
given application.
3.4 OFFSET VOLTAGE
The LMF100’s switched capacitor integrators have a slightly
higher input offset voltage than found in a typical continuous
time active filter integrator. Because of National’s new LMC-
MOS process and new design techniques the internal offsets
have been minimized, compared to the industry standard
MF10. Figure 22 shows an equivalent circuit of the LMF100
from which the output dc offsets can be calculated. Typical
values for these offsets with S
V
V
V
When S
dc offset at the BP output is equal to the input offset of the
lowpass integrator (V
depend on the mode of operation and the resistor ratios, as
described in the following expressions.
Mode 1 and Mode 4
Mode 1a
+
OS1
OS2
OS3
/2 for Single-Supply Operation
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= opamp offset =
=
=
±
±
A/B
30 mV at 50:1 or 100:1
15 mV at 50:1 or 100:1
is tied to V
OS3
−
, V
±
(c) Operational Amplifier with
). The offsets at the other outputs
5 mV
OS2
A/B
will approximately halve. The
tied to V
Divider
+
are:
www.national.com
DS005645-34