LFE2-12E-5FN256C LATTICE SEMICONDUCTOR, LFE2-12E-5FN256C Datasheet - Page 103

• Manufacturer Part Number: LFE2-12E-5FN256C
• Description: IC, LATTICEECP2 FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2r

Specifications of LFE2-12E-5FN256C

• No. Of Logic Blocks: 12000
• No. Of Macrocells: 6000
• No. Of Speed Grades: 5
• No. Of I/o's: 193
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 221Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Descriptions (Cont.)
Lattice Semiconductor
[LOC]_SQ_VCCOBm
[LOC]_SQ_HDOUTNm
[LOC]_SQ_HDOUTPm
[LOC]_SQ_HDINNm
[LOC]_SQ_HDINPm
[LOC]_SQ_VCCTXm
[LOC]_SQ_VCCRXm
1. These signals are relevant for LatticeECP2M family.
2. m defines the associated channel in the Quad.
3. These signals are defined in Quads [LOC] indicates the corner SERDES Quad is located: ULC (upper left), URC (upper right), LLC (lower
4. When placing switching I/Os around these critical pins that are designed to supply the device with the proper reference or supply voltage,
left), LRC (lower right).
care must be given. For more information, refer to technical note TN1159, LatticeECP2/M Pin Assignment Recommendations.
Signal Name
4
4
I/O
—
—
—
O
O
I
I
Output buffer power supply, channel m (1.2V/1.5V). This pin should be left
floating if the channel is unused.
High-speed output, negative channel m
High-speed output, positive channel m
High-speed input, negative channel m
High-speed input, positive channel m
Transmitter power supply, channel m (1.2V). This pin must be tied to 1.2V
even if the channel is unused.
Receiver power supply, channel m (1.2V). This pin must be tied to 1.2V even if
the channel is unused.
4-3
LatticeECP2/M Family Data Sheet
Description
Pinout Information