LFE2-50E-5FN484C LATTICE SEMICONDUCTOR, LFE2-50E-5FN484C Datasheet - Page 88
![no-image](/images/manufacturer_photos/0/3/381/lattice_semiconductor_sml.jpg)
LFE2-50E-5FN484C
Manufacturer Part Number
LFE2-50E-5FN484C
Description
IC, LATTICEECP2 FPGA, 420MHZ, FPBGA-484
Manufacturer
LATTICE SEMICONDUCTOR
Series
LatticeECP2r
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-50E-5FN484C
No. Of Logic Blocks
48000
No. Of Macrocells
24000
No. Of Speed Grades
5
No. Of I/o's
339
Clock Management
DLL, PLL
I/o Supply Voltage
3.465V
Total Ram Bits
387Kbit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-50E-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
DLL Timing
f
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1. CLKOP runs at the same frequency as the input clock.
2. CLKOS minimum frequency is obtained with divide by 4.
3. This is intended to be a “path-matching” design guideline and is not a measurable specification.
Timing v.A 0.11
Parameter
REF
FB
CLKOP
CLKOS
PJIT
CYJIT
DUTY
DUTYTRD
DUTYCIR
SKEW
PWH
PWL
R
INSTB
LOCK
RSWD
PA
RANGE1
RANGE4
, t
F
3
1
2
Input reference clock frequency (on-chip or off-chip)
Feedback clock frequency (on-chip or off-chip)
Output clock frequency, CLKOP
Output clock frequency, CLKOS
Output clock period jitter (clean input)
Output clock cycle to cycle jitter (clean input)
Output clock duty cycle (at 50% levels, 50% duty cycle input clock,
50% duty cycle circuit turned off, time reference delay mode)
Output clock duty cycle (at 50% levels, arbitrary duty cycle input
clock, 50% duty cycle circuit enabled, time reference delay mode)
Output clock duty cycle (at 50% levels, arbitrary duty cycle input
clock, 50% duty cycle circuit enabled, clock injection removal
mode)
Output clock to clock skew between two outputs with the same
phase setting
Input clock minimum pulse width high (at 80% level)
Input clock minimum pulse width low (at 20% level)
Input clock rise and fall time (20% to 80% levels)
Input clock period jitter
DLL lock time
Digital reset minimum pulse width (at 80% level)
Delay step size
Max. delay setting for single delay block (144 taps)
Max. delay setting for four chained delay blocks
Over Recommended Operating Conditions
Description
3-37
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
18,500
2.376
9.504
Min.
16.5
100
100
100
750
750
25
35
40
40
—
—
—
3
Typ.
42
24
—
—
—
—
—
—
—
—
—
—
—
—
6
34.214
+/-250
8.553
Max.
59.4
500
500
500
500
250
250
100
65
60
60
—
—
—
—
1
ps p-p
ps p-p
cycles
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ns
ps
ns
ps
ns
ns
%
%
%
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