LFE2M50E-5FN900C LATTICE SEMICONDUCTOR, LFE2M50E-5FN900C Datasheet - Page 7
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LFE2M50E-5FN900C
Manufacturer Part Number
LFE2M50E-5FN900C
Description
IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-900
Manufacturer
LATTICE SEMICONDUCTOR
Series
LatticeECP2Mr
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2M50E-5FN900C
No. Of Logic Blocks
48000
No. Of Macrocells
24000
No. Of Speed Grades
5
No. Of I/o's
410
Clock Management
DLL, PLL
I/o Supply Voltage
3.465V
Total Ram Bits
4147Kbit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M50E-5FN900C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 2-4. Slice Diagram
Table 2-2. Slice Signal Descriptions
1. See Figure 2-4 for connection details.
2. Requires two PFUs.
Function
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Routing
From
Inter-PFU signal
Inter-slice signal
Inter-slice signal
Inter-PFU signal
Multi-purpose
Multi-purpose
Control signal
Control signal
Control signal
Data signals
Data signals
Data signals
Data signals
Data signal
Data signal
FXB
FXA
CLK
LSR
Type
M1
M0
CE
A1
B1
C1
D1
A0
B0
C0
D0
* Not in Slice 3
For Slices 0 and 2, memory control signals are generated from Slice 1 as follows:
WCK is CLK
WRE is from LSR
DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data
WAD [A:D] is a 4bit address from slice 1 LUT input
A0, B0, C0, D0
A1, B1, C1, D1
Signal Names
Q0, Q1
F0, F1
OFX0
OFX1
FCO
LSR
CLK
FXA
FXB
M0
M1
CE
FC
FCO To Different Slice/PFU
FCI From Different Slice/PFU
LUT4 &
CARRY*
LUT4 &
CARRY*
Inputs to LUT4
Inputs to LUT4
Multipurpose Input
Multipurpose Input
Clock Enable
Local Set/Reset
System Clock
Fast Carry-in
Intermediate signal to generate LUT6 and LUT7
Intermediate signal to generate LUT6 and LUT7
LUT4 output register bypass signals
Register outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT8
Slice 2 of each PFU is the fast carry chain output
CO
CO
CI
CI
2-4
F/SUM
F/SUM
1
LUT5
LatticeECP2/M Family Data Sheet
Mux
Description
2
MUX depending on the slice
SLICE
D
D
FF*
FF*
Routing
OFX1
F1
Q1
To
OFX0
F0
Q0
1
Architecture
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