EPM7256AEQC208-10N Altera, EPM7256AEQC208-10N Datasheet - Page 8

• Manufacturer Part Number: EPM7256AEQC208-10N
• Description: IC PLD EEPROM 256 MACROCELL 10NS QFP-208
• Manufacturer: Altera
• Series: MAX 7000AEr

Specifications of EPM7256AEQC208-10N

• Cpld Type: EEPROM
• No. Of Macrocells: 256
• No. Of I/o's: 164
• Propagation Delay: 10ns
• Global Clock Setup Time: 3.9ns
• Frequency: 90.9MHz
• Supply Voltage Range: 3V To 3.6V
• Family Name: MAX 7000A
• Memory Type: EEPROM
• # Macrocells: 256
• Number Of Usable Gates: 5000
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 16
• # I/os (max): 164
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MAX 7000A Programmable Logic Device Data Sheet
Figure 2. MAX 7000A Macrocell
8
36 Signals
from PIA
LAB Local Array
Product Terms
16 Expander
Macrocells
MAX 7000A macrocells can be individually configured for either
sequential or combinatorial logic operation. The macrocells consist of
three functional blocks: the logic array, the product-term select matrix,
and the programmable register.
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register preset, clock, and clock enable control
functions.
Two kinds of expander product terms (“expanders”) are available to
supplement macrocell logic resources:
The Altera development system automatically optimizes product-term
allocation according to the logic requirements of the design.
Shareable expanders, which are inverted product terms that are fed
back into the logic array
Parallel expanders, which are product terms borrowed from adjacent
macrocells
Product-
Select
Matrix
Term
Shared Logic
Expanders
Parallel Logic
Expanders
(from other
macrocells)
Global
Clear
Select
Clear
Clocks
Global
2
Figure 2
VCC
Enable
Clock/
Select
shows a MAX 7000A macrocell.
Fast Input
Select
ENA
D/T
CLRN
PRN
To PIA
Q
Altera Corporation
Programmable
Register
Register
Bypass
From
I/O pin
To I/O
Control
Block