GAL16V8D-15QPN LATTICE SEMICONDUCTOR, GAL16V8D-15QPN Datasheet - Page 15

• Manufacturer Part Number: GAL16V8D-15QPN
• Description: IC, GAL, 15NS, DIP-20
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of GAL16V8D-15QPN

• Logic Type: EEPLD
• Propagation Delay: 15ns
• No. Of I/o's: 8
• Frequency: 62.5MHz
• Supply Current Max: 55mA
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +75°C
• Logic Case Style: DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GAL16V8D-3 Output Load Conditions (see figure at right)
An electronic signature is provided in every GAL16V8 device. It
contains 64 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.
NOTE: The electronic signature is included in checksum calcula-
tions. Changing the electronic signature will alter the checksum.
A security cell is provided in the GAL16V8 devices to prevent un-
authorized copying of the array patterns. Once programmed, this
cell prevents further read access to the functional bits in the device.
This cell can only be erased by re-programming the device, so the
original configuration can never be examined once this cell is pro-
grammed. The Electronic Signature is always available to the user,
regardless of the state of this control cell.
GAL16V8 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias minimizes the
potential of latch-up caused by negative input undershoots. Ad-
ditionally, outputs are designed with n-channel pull-ups instead of
the traditional p-channel pull-ups in order to eliminate latch-up due
to output overshoots.
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers. Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.
Switching Test Conditions (Continued)
Electronic Signature
Security Cell
Latch-Up Protection
Device Programming
Test Condition
A
B
C
High Z to Active High at 1.9V
High Z to Active Low at 1.0V
Active High to High Z at 1.9V
Active Low to High Z at 1.0V
50
50
50
50
50
R
1
35pF
35pF
35pF
35pF
35pF
C
L
15
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
GAL16V8 devices include circuitry that allows each registered
output to be synchronously set either high or low. Thus, any present
state condition can be forced for test sequencing. If necessary,
approved GAL programmers capable of executing text vectors
perform output register preload automatically.
GAL16V8 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.
The GAL16V8 input and I/O pins have built-in active pull-ups. As
a result, unused inputs and I/O's will float to a TTL "high" (logical
"1"). Lattice Semiconductor recommends that all unused inputs
and tri-stated I/O pins be connected to another active input, V
or Ground. Doing this will tend to improve noise immunity and re-
duce I
Output Register Preload
Input Buffers
FROM OUTPUT (O/Q)
UNDER TEST
CC
- 4 0
- 2 0
- 6 0
*C
for the device.
0
0
L
includes test fixture and probe capacitance.
Specifications GAL16V8
Typical Input Pull-up Characteristic
1 . 0
In p u t V o lt ag e ( V o lt s)
TEST POINT
2 . 0
Z
0
= 50 , C
3 . 0
L
= 35pF*
4 . 0
+1.45V
5 . 0
R
1
CC
,