74HCT165N NXP Semiconductors, 74HCT165N Datasheet - Page 2

• Manufacturer Part Number: 74HCT165N
• Description: IC, 74HCT CMOS, 74HCT165, DIP16, 5V
• Manufacturer: NXP Semiconductors

Specifications of 74HCT165N

• No. Of Elements: 1
• Ic Output Type: Standard
• Logic Case Style: DIP
• No. Of Pins: 16
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +125°C
• Svhc: No
• Logic Type: Shift Register
• Shift Register Function: Parallel To Serial
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT165 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT165 are 8-bit parallel-load or serial-in shift
registers with complementary serial outputs (Q
Q
(PL) input is LOW, parallel data from the D
D
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
t
f
C
C
PHL
max
7
7
Asynchronous 8-bit parallel load
Synchronous serial input
Output capability: standard
I
8-bit parallel-in/serial-out shift register
I
PD
) available from the last stage. When the parallel load
SYMBOL
CC
inputs are loaded into the register asynchronously.
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
CC
PD
= input frequency in MHz
L
category: MSI
= output frequency in MHz
(C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
propagation delay
maximum clock frequency
input capacitance
power dissipation capacitance per
package
2
CP to Q
PL to Q
D
= 25 C; t
7
V
f
o
to Q
CC
) = sum of outputs
2
7,
7,
7,
Q
f
PARAMETER
Q
r
Q
i
= t
7
7
7
I
I
f
= GND to V
= GND to V
= 6 ns
(C
L
V
CC
2
0
CC
CC
to
f
o
7
) where:
and
1.5 V
C
notes 1 and 2
L
= 15 pF; V
CONDITIONS
2
.
When PL is HIGH, data enters the register serially at the
D
(Q
transition. This feature allows parallel-to-serial converter
expansion by tying the Q
succeeding stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take
place while CP HIGH for predictable operation. Either the
CP or the CE should be HIGH before the
LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
APPLICATIONS
s
D
Parallel-to-serial data conversion
0
input and shifts one place to the right
in W):
CC
Q
1
= 5 V
Q
2
, etc.) with each positive-going clock
16
15
11
56
3.5
35
HC
7
TYPICAL
output to the D
14
17
11
48
3.5
35
74HC/HCT165
Product specification
HCT
S
input of the
ns
ns
ns
MHz
pF
pF
UNIT