CAT24C32LI-G CATALYST SEMICONDUCTOR, CAT24C32LI-G Datasheet - Page 8

• Manufacturer Part Number: CAT24C32LI-G
• Description: IC, EEPROM, 32KBIT, SERIAL, 400KHZ DIP-8
• Manufacturer: CATALYST SEMICONDUCTOR

Specifications of CAT24C32LI-G

• Memory Size: 32Kbit
• Memory Configuration: 4K X 8
• Ic Interface Type: I2C
• Clock Frequency: 400kHz
• Supply Voltage Range: 1.7V To 5.5V
• Memory Case Style: DIP
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Immediate Read
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 10). The Slave then returns to Standby mode.
Selective Read
address must first be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends two
address bytes to the Slave. Rather than completing the Byte
To read data from memory, the Master creates a START
To read data residing at a specific address, the selected
BUS ACTIVITY:
BUS ACTIVITY:
MASTER
MASTER
SLAVE
SLAVE
SCL
SDA
S
S
T
A
R
T
ADDRESS
SLAVE
ADDRESS
SLAVE
A
C
K
BUS ACTIVITY
Figure 10. Immediate Read Sequence and Timing
A
C
K
BYTE
DATA
MASTER
n
Figure 12. Sequential Read Sequence
SLAVE
Figure 11. Selective Read Sequence
ADDRESS
DATA OUT
BYTE
8th Bit
8
READ OPERATIONS
A
C
K
R
S
S
T
A
T
http://onsemi.com
ADDRESS
BYTE
DATA
A
C
K
SLAVE
n+1
ADDRESS
8
BYTE
Write sequence by sending data, the Master then creates a
START condition and broadcasts a Slave address with the
R/W bit set to ‘1’. The Slave responds with ACK after every
byte sent by the Master and then sends out data residing at
the selected address. After receiving the data, the Master
responds with NoACK and then terminates the session by
creating a STOP condition on the bus (Figure 11).
Sequential Read
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 12). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory.
A
C
K
If, after receiving data sent by the Slave, the Master
A
C
K
NO ACK
9
BYTE
DATA
A
C
K
BYTE
DATA
n+2
S
S
T
A
R
T
ADDRESS
SLAVE
A
C
K
N
O
C
A
K
P
O
S
T
P
A
C
K
STOP
BYTE
DATA
n+x
BYTE
DATA
O
N
A
C
K
O
S
P
P
T
O
N
A
C
K
O
S
T
P
P